TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
EDN 21 21 100.00
ENTROPY_SRC 19 22 86.36
HMAC 28 28 100.00
I2C 44 50 88.00
KEYMGR 29 30 96.67
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 37 40 92.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 39 39 100.00
OTBN 40 41 97.56
PATTGEN 16 18 88.89
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_JTAG_INTERFACE 48 53 90.57
RV_TIMER 19 19 100.00
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
SYSRST_CTRL 25 27 92.59
UART 26 27 96.30
USBDEV 96 99 96.97
GPIO 26 27 96.30
ALERT_HANDLER 22 26 84.62
CLKMGR 26 27 96.30
FLASH_CTRL 57 78 73.08
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 27 28 96.43
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 287 325 88.31