TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 24 25 96.00
AES/UNMASKED 31 32 96.88
AES/MASKED 30 32 93.75
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
EDN 21 21 100.00
ENTROPY_SRC/RNG_4BITS 18 22 81.82
HMAC 28 28 100.00
I2C 44 50 88.00
KEYMGR 29 30 96.67
KMAC/MASKED 38 40 95.00
KMAC/UNMASKED 38 40 95.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 38 39 97.44
LC_CTRL/VOLATILE_UNLOCK_ENABLED 38 39 97.44
OTBN 39 41 95.12
PATTGEN 15 18 83.33
PRIM_ALERT 4 4 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 19 19 100.00
RV_DM/USE_JTAG_INTERFACE 45 53 84.91
RV_TIMER 19 19 100.00
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
SYSRST_CTRL 26 27 96.30
UART 25 27 92.59
USBDEV 97 99 97.98
GPIO 26 27 96.30
ALERT_HANDLER 22 26 84.62
CLKMGR 27 27 100.00
FLASH_CTRL 60 78 76.92
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 28 28 100.00
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 268 325 82.46