TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Wednesday November 05 2025 19:20:47 UTC

GitHub Revision: 9baed2b

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 24 25 96.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 19 19 100.00
EDN 21 21 100.00
ENTROPY_SRC/RNG_4BITS 22 22 100.00
HMAC 28 28 100.00
I2C 42 50 84.00
KEYMGR 30 30 100.00
KMAC/MASKED 40 40 100.00
KMAC/UNMASKED 38 40 95.00
LC_CTRL/VOLATILE_UNLOCK_DISABLED 36 39 92.31
LC_CTRL/VOLATILE_UNLOCK_ENABLED 33 39 84.62
OTBN 19 41 46.34
PATTGEN 15 18 83.33
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 19 19 100.00
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 43 53 81.13
RV_TIMER 16 19 84.21
SPI_HOST 25 26 96.15
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 29 31 93.55
SRAM_CTRL/RET 29 31 93.55
SYSRST_CTRL 27 27 100.00
UART 25 27 92.59
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 25 26 96.15
CLKMGR 27 27 100.00
FLASH_CTRL 77 79 97.47
OTP_CTRL 27 30 90.00
PWM 17 17 100.00
PWRMGR 25 28 89.29
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 274 326 84.05