TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday June 22 2025 00:12:31 UTC

GitHub Revision: 4a542c3

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 896 920 97.39 97.40
AES/UNMASKED 1525 1602 95.19 97.23
AES/MASKED 1553 1602 96.94 98.41
AON_TIMER 315 315 100.00 99.29
CSRNG 1548 1630 94.97 97.59
EDN 1119 1130 99.03 96.04
ENTROPY_SRC/RNG_4BITS 1700 2570 66.15 93.25
HMAC 821 821 100.00 91.65
I2C 1865 2042 91.33 87.86
KEYMGR 1062 1110 95.68 97.73
KMAC/MASKED 927 940 98.62 95.40
KMAC/UNMASKED 905 940 96.28 93.82
LC_CTRL/VOLATILE_UNLOCK_DISABLED 1003 1030 97.38 90.30
LC_CTRL/VOLATILE_UNLOCK_ENABLED 1000 1030 97.09 90.41
OTBN 568 585 97.09 99.04
PATTGEN 447 570 78.42 98.72
PRIM_ALERT 77 80 96.25 94.85
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
ROM_CTRL/32KB 260 266 97.74 99.66
ROM_CTRL/64KB 266 266 100.00 99.63
RV_DM/USE_JTAG_INTERFACE 383 483 79.30 75.61
RV_TIMER 350 350 100.00 96.44
SPI_HOST 839 840 99.88 95.20
SPI_DEVICE/1R1W 1128 1151 98.00 92.80
SPI_DEVICE/2P 1151 1151 100.00 93.34
SRAM_CTRL/MAIN 1168 1190 98.15 96.08
SRAM_CTRL/RET 1169 1190 98.24 96.05
SYSRST_CTRL 900 932 96.57 96.58
UART 1248 1320 94.55 95.03
USBDEV 3905 3965 98.49 97.38
GPIO 970 1020 95.10 96.61
ALERT_HANDLER 658 850 77.41 98.84
CLKMGR 955 960 99.48 97.07
FLASH_CTRL 1005 1281 78.45 96.27
OTP_CTRL 1163 1343 86.60 93.12
PWM 115 276 41.67 99.21
PWRMGR 1063 1070 99.35 98.11
RSTMGR_CNSTY_CHK 10 10 100.00 95.87
RSTMGR 620 620 100.00 99.49
XBAR_MAIN 900 900 100.00 99.18
XBAR_PERI 900 900 100.00 99.20
CHIP 2725 2955 92.22 95.12