TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Monday October 20 2025 17:15:22 UTC

GitHub Revision: cf33148

Branch: master

Name Passing Total Pass Rate
TL_AGENT 1 1 100.00
ADC_CTRL 25 25 100.00
AES/UNMASKED 31 32 96.88
AES/MASKED 31 32 96.88
AON_TIMER 23 23 100.00
CSRNG 18 19 94.74
EDN 20 21 95.24
ENTROPY_SRC/RNG_4BITS 22 22 100.00
HMAC 28 28 100.00
I2C 45 50 90.00
KEYMGR 30 30 100.00
KMAC/MASKED 39 40 97.50
KMAC/UNMASKED 39 40 97.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED 37 39 94.87
LC_CTRL/VOLATILE_UNLOCK_ENABLED 37 39 94.87
OTBN 20 41 48.78
PATTGEN 17 18 94.44
PRIM_ALERT 5 5 100.00
PRIM_ESC 1 1 100.00
PRIM_LFSR 4 4 100.00
PRIM_PRESENT 1 1 100.00
PRIM_PRINCE 1 1 100.00
ROM_CTRL/32KB 18 19 94.74
ROM_CTRL/64KB 18 19 94.74
RV_DM/USE_JTAG_INTERFACE 44 53 83.02
RV_TIMER 16 19 84.21
SPI_HOST 26 26 100.00
SPI_DEVICE/1R1W 31 33 93.94
SPI_DEVICE/2P 33 33 100.00
SRAM_CTRL/MAIN 30 31 96.77
SRAM_CTRL/RET 30 31 96.77
SYSRST_CTRL 27 27 100.00
UART 24 27 88.89
USBDEV 98 100 98.00
GPIO 26 27 96.30
ALERT_HANDLER 24 26 92.31
CLKMGR 26 27 96.30
FLASH_CTRL 58 78 74.36
OTP_CTRL 27 30 90.00
PWM 8 17 47.06
PWRMGR 15 28 53.57
RSTMGR_CNSTY_CHK 1 1 100.00
RSTMGR 19 19 100.00
XBAR_MAIN 18 18 100.00
XBAR_PERI 18 18 100.00
CHIP 283 326 86.81