TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday May 04 2025 00:13:41 UTC

GitHub Revision: 77a9e5b

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 896 920 97.39 97.67
AES/UNMASKED 1551 1602 96.82 97.29
AES/MASKED 1553 1602 96.94 98.38
AON_TIMER 315 315 100.00 100.00
CSRNG 1619 1630 99.33 97.73
EDN 1111 1130 98.32 95.67
ENTROPY_SRC 1703 2570 66.26 96.11
HMAC 821 821 100.00 92.06
I2C 1840 2042 90.11 87.80
KEYMGR 1064 1110 95.86 97.80
KMAC/MASKED 923 940 98.19 94.84
KMAC/UNMASKED 913 940 97.13 94.02
LC_CTRL/VOLATILE_UNLOCK_DISABLED 996 1030 96.70 90.31
LC_CTRL/VOLATILE_UNLOCK_ENABLED 1004 1030 97.48 90.22
OTBN 566 585 96.75 99.06
PATTGEN 455 570 79.82 98.88
PRIM_ALERT 79 80 98.75 95.19
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
ROM_CTRL/32KB 251 266 94.36 98.61
ROM_CTRL/64KB 249 266 93.61 98.57
RV_DM/USE_JTAG_INTERFACE 387 483 80.12 76.01
RV_TIMER 350 350 100.00 100.00
SPI_HOST 838 840 99.76 96.31
SPI_DEVICE/1R1W 1130 1151 98.18 94.44
SPI_DEVICE/2P 1150 1151 99.91 94.47
SRAM_CTRL/MAIN 1164 1190 97.82 96.06
SRAM_CTRL/RET 1163 1190 97.73 96.01
SYSRST_CTRL 894 932 95.92 97.57
UART 1312 1320 99.39 97.76
USBDEV 3905 3965 98.49 97.07
GPIO 970 1020 95.10 98.85
ALERT_HANDLER 666 850 78.35 98.91
CLKMGR 954 960 99.38 97.01
FLASH_CTRL 995 1281 77.67 94.97
OTP_CTRL 1155 1343 86.00 94.21
PWM 115 276 41.67 99.23
PWRMGR 1060 1070 99.07 98.02
RSTMGR_CNSTY_CHK 10 10 100.00 95.87
RSTMGR 620 620 100.00 99.49
XBAR_MAIN 900 900 100.00 99.17
XBAR_PERI 900 900 100.00 99.14
CHIP 2755 2955 93.23 95.58