TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday October 05 2025 00:13:39 UTC

GitHub Revision: 7302728

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 893 920 97.07 97.41
AES/UNMASKED 1555 1602 97.07 97.25
AES/MASKED 1560 1602 97.38 98.39
AON_TIMER 315 315 100.00 98.89
CSRNG 1620 1630 99.39 97.64
EDN 1109 1130 98.14 95.47
ENTROPY_SRC/RNG_4BITS 2553 2570 99.34 94.13
HMAC 821 821 100.00 98.77
I2C 1788 2042 87.56 84.02
KEYMGR 1083 1110 97.57 97.38
KMAC/MASKED 935 940 99.47 95.35
KMAC/UNMASKED 926 940 98.51 93.54
LC_CTRL/VOLATILE_UNLOCK_DISABLED 992 1030 96.31 90.02
LC_CTRL/VOLATILE_UNLOCK_ENABLED 993 1030 96.41 90.09
OTBN 292 585 49.91 94.20
PATTGEN 463 570 81.23 98.53
PRIM_ALERT 96 100 96.00 95.19
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
ROM_CTRL/32KB 261 266 98.12 99.14
ROM_CTRL/64KB 262 266 98.50 99.14
RV_DM/USE_JTAG_INTERFACE 345 483 71.43 81.71
RV_TIMER 312 350 89.14 95.77
SPI_HOST 837 840 99.64 95.10
SPI_DEVICE/1R1W 1130 1151 98.18 92.62
SPI_DEVICE/2P 1150 1151 99.91 93.16
SRAM_CTRL/MAIN 1169 1190 98.24 95.66
SRAM_CTRL/RET 1158 1190 97.31 95.64
SYSRST_CTRL 915 932 98.18 97.47
UART 1249 1320 94.62 94.53
USBDEV 3910 3970 98.49 96.80
GPIO 970 1020 95.10 96.08
ALERT_HANDLER 765 850 90.00 98.84
CLKMGR 956 960 99.58 96.92
FLASH_CTRL 1014 1281 79.16 96.32
OTP_CTRL 1156 1343 86.08 87.70
PWM 115 276 41.67 99.11
PWRMGR 496 1070 46.36 95.36
RSTMGR_CNSTY_CHK 10 10 100.00 95.87
RSTMGR 620 620 100.00 99.27
XBAR_MAIN 900 900 100.00 99.03
XBAR_PERI 900 900 100.00 98.97
CHIP 2756 2956 93.23 89.78