Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	135	233	57.94	67.50	96.14	13.66	92.71	-	98.86	97.40	87.39	99.76	97.30
AES/MASKED	1003	1110	90.36	97.81	96.76	98.28	98.38	96.88	97.77	92.67	-	98.08	98.52
AES/UNMASKED	986	1110	88.83	96.14	93.00	97.32	98.11	93.96	95.22	87.58	-	98.08	91.11
ALERT_HANDLER	529	593	89.21	99.06	98.88	99.43	98.87	-	99.99	99.99	97.42	97.01	100.00
AON_TIMER	180	180	100.00	99.05	99.05	100.00	98.10	-	99.09	98.56	99.05	99.50	-
CHIP	1710	2005	85.29	94.16	85.19	99.43	97.87	-	94.64	94.40	92.74	87.01	57.14
CLKMGR	239	273	87.55	93.87	98.54	87.31	95.76	-	99.07	98.74	95.68	99.19	100.00
CSRNG	1360	1403	96.94	94.63	96.20	90.97	96.72	98.53	99.54	96.38	-	93.64	95.24
EDN/EDN0	672	688	97.67	95.28	95.58	92.66	97.61	-	98.91	96.51	94.02	97.07	91.40
EDN/EDN1	678	688	98.55	95.68	95.90	92.44	98.70	-	98.48	94.59	94.85	96.15	95.45
ENTROPY_SRC/RNG_4BITS	2397	2453	97.72	91.08	90.50	92.75	89.98	95.18	97.82	88.06	-	79.22	96.88
FLASH_CTRL	1141	1154	98.87	96.97	95.50	98.39	97.02	-	96.10	97.45	94.85	96.60	92.52
GPIO	232	253	91.70	97.78	94.91	100.00	98.42	-	99.76	99.80	99.57	80.52	-
HMAC	693	694	99.86	98.84	99.20	99.73	97.60	-	99.74	99.67	96.57	100.00	100.00
I2C	586	755	77.62	88.81	80.37	89.22	96.83	-	97.25	93.75	89.18	74.04	47.62
KEYMGR	634	653	97.09	95.90	98.84	91.13	97.72	-	99.20	99.00	98.08	97.90	100.00
KMAC/MASKED	337	540	62.41	86.26	74.15	86.17	98.45	-	97.15	92.90	90.34	29.62	60.76
KMAC/UNMASKED	342	540	63.33	85.34	71.99	85.65	98.39	-	95.58	92.11	90.49	27.75	54.01
LC_CTRL/VOLATILE_UNLOCK_DISABLED	518	523	99.04	92.47	86.09	96.62	94.69	-	97.28	94.00	81.70	88.33	69.16
LC_CTRL/VOLATILE_UNLOCK_ENABLED	518	523	99.04	92.51	86.12	96.44	94.97	-	97.26	93.95	81.89	88.33	69.16
OTBN	425	436	97.48	93.31	82.70	100.00	97.23	97.86	98.04	82.67	-	82.50	67.61
OTP_CTRL	789	903	87.38	91.21	85.99	92.23	95.40	-	90.33	86.85	94.05	95.72	63.02
PRIM_ALERT	54	60	90.00	91.18	96.31	-	86.05	-	100.00	95.83	100.00	100.00	85.71
PRIM_ESC	20	20	100.00	89.45	93.71	-	85.19	-	95.41	88.89	87.80	100.00	96.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	10	10	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	251	273	91.94	98.50	97.54	99.01	98.96	-	99.09	96.37	96.61	99.62	96.00
ROM_CTRL/32KB	153	156	98.08	98.48	98.63	99.28	97.53	-	99.46	100.00	98.37	95.33	100.00
ROM_CTRL/64KB	154	156	98.72	98.48	98.72	99.05	97.68	-	99.46	100.00	98.81	95.34	100.00
RSTMGR	148	148	100.00	99.12	99.66	98.76	98.93	-	99.51	99.83	99.31	100.00	-
RSTMGR_CNSTY_CHK	10	10	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	334	368	90.76	78.05	88.70	49.59	95.87	-	96.25	90.50	90.42	71.51	94.81
RV_TIMER	181	223	81.17	97.40	94.66	99.12	98.41	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	395	416	94.95	95.17	91.48	98.51	95.52	-	98.90	98.30	96.53	74.30	89.36
SPI_HOST	219	220	99.55	92.89	91.32	90.76	96.60	97.01	98.76	93.45	-	73.07	100.00
SRAM_CTRL/MAIN	224	248	90.32	96.85	95.85	96.60	98.10	96.30	97.05	94.50	-	91.84	100.00
SRAM_CTRL/RET	222	248	89.52	92.46	82.51	96.80	98.08	94.03	95.21	89.83	-	78.32	66.67
SYSRST_CTRL	405	410	98.78	96.13	97.77	92.05	98.56	-	98.88	98.96	98.06	100.00	92.95
TL_AGENT	10	10	100.00	-	-	-	-	-	-	-	-	-	-
UART	438	453	96.69	96.87	92.64	99.41	98.56	-	99.48	98.14	98.25	74.67	-
USBDEV	1754	1780	98.54	97.71	97.30	98.55	97.29	-	98.81	98.39	95.68	97.03	96.61
XBAR_MAIN	450	450	100.00	99.36	99.09	100.00	99.00	-	100.00	100.00	96.72	99.63	-
XBAR_PERI	450	450	100.00	99.42	99.16	100.00	99.09	-	100.00	100.00	96.64	100.00	-

Simulation Results: top_earlgrey_batch_sim