Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	232	233	99.57	71.62	98.54	19.39	96.92	-	99.05	98.51	95.12	100.00	100.00
AES/MASKED	1006	1110	90.63	97.93	96.57	98.85	98.38	96.91	97.77	92.75	-	97.99	97.78
AES/UNMASKED	994	1110	89.55	96.08	93.00	97.13	98.11	93.88	95.11	87.69	-	98.08	91.11
ALERT_HANDLER	516	593	87.02	99.01	98.91	99.24	98.89	-	99.99	99.99	97.43	97.12	100.00
AON_TIMER	180	180	100.00	99.09	99.17	100.00	98.10	-	99.09	98.56	99.05	100.00	-
CHIP	1654	1945	85.04	91.12	77.23	98.80	97.34	-	93.99	94.38	92.41	72.06	33.33
CLKMGR	237	273	86.81	94.19	98.85	87.82	95.90	-	99.29	99.06	95.89	100.00	100.00
CSRNG	1371	1403	97.72	94.58	96.17	90.62	96.94	98.49	99.50	96.30	-	93.64	95.24
EDN/EDN0	670	688	97.38	95.61	95.47	92.66	98.70	-	98.91	96.51	93.96	97.12	90.86
EDN/EDN1	680	688	98.84	95.24	96.15	92.44	97.14	-	98.48	94.59	94.92	96.15	96.59
ENTROPY_SRC/RNG_4BITS	2319	2453	94.54	91.08	90.52	92.75	89.98	95.18	97.82	88.06	-	79.30	96.88
GPIO	232	253	91.70	97.25	94.91	100.00	96.84	-	99.76	99.80	99.57	80.52	-
HMAC	694	694	100.00	95.14	88.30	99.52	97.60	-	99.64	99.35	96.36	46.17	100.00
I2C	595	755	78.81	89.13	80.50	89.22	97.67	-	97.31	93.97	88.99	74.04	48.21
KEYMGR_DPE/EARLGREY	105	143	73.43	65.93	83.53	16.58	97.67	-	97.64	94.82	90.02	59.49	75.68
KMAC/MASKED	317	540	58.70	82.25	67.95	84.30	94.51	-	97.42	91.36	87.33	23.15	40.51
KMAC/UNMASKED	313	540	57.96	80.47	64.34	82.76	94.31	-	95.65	88.81	85.03	21.54	30.66
LC_CTRL/VOLATILE_UNLOCK_DISABLED	515	523	98.47	92.25	85.87	96.06	94.83	-	97.28	94.05	81.49	88.33	68.22
LC_CTRL/VOLATILE_UNLOCK_ENABLED	515	523	98.47	92.43	85.91	96.42	94.97	-	97.26	94.00	81.76	88.33	68.22
OTBN	420	436	96.33	94.81	87.07	100.00	97.35	99.33	99.54	95.19	-	85.93	67.61
OTP_CTRL	787	903	87.15	90.99	85.24	92.19	95.53	-	90.14	86.65	93.95	92.61	62.85
PRIM_ALERT	57	60	95.00	91.54	97.02	-	86.05	-	100.00	95.83	100.00	100.00	89.29
PRIM_ESC	20	20	100.00	89.45	93.71	-	85.19	-	95.41	88.89	87.80	100.00	96.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	89.63	79.26	-	100.00	-	90.41	75.00	75.00	76.63	-
PRIM_PRINCE	10	10	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	217	273	79.49	98.41	97.54	99.01	98.69	-	99.09	96.38	96.61	99.62	96.00
ROM_CTRL/192KB	154	156	98.72	98.40	98.53	99.28	97.39	-	99.21	99.28	98.81	95.34	100.00
RSTMGR	148	148	100.00	99.12	99.66	98.76	98.93	-	99.51	99.83	99.31	100.00	-
RSTMGR_CNSTY_CHK	10	10	100.00	97.81	95.61	-	100.00	-	98.46	98.39	88.89	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	328	368	89.13	77.58	88.58	48.30	95.87	-	96.20	89.74	90.56	71.58	94.81
RV_TIMER	204	223	91.48	97.50	94.66	99.12	98.73	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	394	416	94.71	95.28	91.48	98.96	95.40	-	98.90	98.27	96.56	74.30	89.36
SPI_HOST	218	220	99.09	92.95	91.30	90.76	96.79	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	232	248	93.55	96.56	95.18	96.40	98.10	94.48	95.64	92.86	-	92.22	100.00
SRAM_CTRL/RET	231	248	93.15	92.14	81.75	96.60	98.08	92.19	93.78	88.23	-	78.32	66.67
SYSRST_CTRL	403	410	98.29	94.71	98.63	86.55	98.95	-	99.46	99.52	98.01	100.00	96.15
TL_AGENT	10	10	100.00	-	-	-	-	-	-	-	-	-	-
UART	441	453	97.35	96.78	92.64	99.44	98.27	-	99.48	98.14	98.25	74.67	-
USBDEV	1756	1780	98.65	97.60	96.86	98.64	97.29	-	98.76	98.18	95.39	97.03	94.92
XBAR_MAIN	450	450	100.00	99.25	99.16	100.00	98.60	-	100.00	100.00	97.26	99.37	-
XBAR_PERI	450	450	100.00	99.59	99.13	100.00	99.65	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim