Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	220	233	94.42	71.57	98.53	19.26	96.92	-	99.05	98.51	95.08	100.00	100.00
AES/MASKED	1020	1110	91.89	97.93	96.56	98.85	98.38	96.88	97.73	92.67	-	98.08	97.78
AES/UNMASKED	1006	1110	90.63	95.81	92.94	96.56	97.92	93.81	95.12	87.54	-	97.99	91.11
ALERT_HANDLER	519	593	87.52	98.90	98.77	99.04	98.89	-	99.99	99.99	97.45	96.40	100.00
AON_TIMER	179	180	99.44	99.09	99.17	100.00	98.10	-	99.09	98.56	99.05	100.00	-
CHIP	1680	1945	86.38	91.12	77.31	98.83	97.22	-	94.04	94.47	92.66	72.04	33.33
CLKMGR	272	273	99.63	94.39	98.87	87.82	96.47	-	99.29	99.06	95.98	100.00	100.00
CSRNG	1391	1403	99.14	95.26	96.19	92.43	97.16	98.50	99.54	96.32	-	93.64	95.24
EDN/EDN0	687	688	99.85	95.74	95.68	93.06	98.48	-	98.91	96.51	93.91	97.12	91.94
EDN/EDN1	687	688	99.85	95.50	96.10	92.23	98.18	-	98.48	94.59	94.69	96.15	96.59
ENTROPY_SRC/RNG_4BITS	2317	2453	94.46	91.09	90.46	92.83	89.98	95.16	97.82	88.01	-	79.12	96.88
GPIO	230	253	90.91	97.88	94.91	100.00	98.73	-	99.76	99.80	99.57	80.52	-
HMAC	694	694	100.00	94.94	87.70	99.52	97.60	-	99.64	99.35	96.30	46.17	97.06
I2C	578	755	76.56	89.09	80.37	89.22	97.67	-	97.25	93.83	89.10	74.04	47.62
KEYMGR_DPE/EARLGREY	104	143	72.73	65.91	83.46	16.61	97.67	-	97.64	94.82	89.68	59.49	75.68
KMAC/MASKED	311	540	57.59	82.33	67.18	85.29	94.51	-	97.37	90.93	87.10	23.17	37.34
KMAC/UNMASKED	312	540	57.78	80.67	64.95	83.33	93.72	-	96.02	89.80	86.74	21.54	30.66
LC_CTRL/VOLATILE_UNLOCK_DISABLED	489	523	93.50	92.20	85.84	96.06	94.69	-	97.28	93.90	81.49	88.33	68.22
LC_CTRL/VOLATILE_UNLOCK_ENABLED	491	523	93.88	92.41	86.20	96.06	94.97	-	97.26	94.29	81.97	88.33	69.16
OTBN	414	443	93.45	93.01	82.58	100.00	96.45	97.79	98.00	82.17	-	82.55	67.61
OTP_CTRL	620	903	68.66	90.66	85.41	91.11	95.47	-	90.24	86.75	94.06	92.82	63.19
PRIM_ALERT	59	60	98.33	91.33	96.61	-	86.05	-	100.00	95.83	97.92	100.00	89.29
PRIM_ESC	20	20	100.00	89.45	93.71	-	85.19	-	95.41	88.89	87.80	100.00	96.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	89.63	79.26	-	100.00	-	90.41	75.00	75.00	76.63	-
PRIM_PRINCE	10	10	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	206	273	75.46	97.91	95.75	99.01	98.96	-	99.09	96.38	96.32	90.96	96.00
ROM_CTRL/192KB	152	156	97.44	98.49	98.51	99.28	97.68	-	99.21	99.64	98.37	95.34	100.00
RSTMGR	148	148	100.00	98.86	99.64	98.01	98.93	-	99.51	99.83	99.24	100.00	-
RSTMGR_CNSTY_CHK	8	10	80.00	97.81	95.61	-	100.00	-	98.46	98.39	88.89	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	329	368	89.40	85.72	88.09	73.28	95.79	-	96.15	89.57	90.69	71.83	92.21
RV_TIMER	204	223	91.48	97.30	94.66	98.82	98.41	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	394	416	94.71	95.25	91.47	98.76	95.52	-	98.89	98.25	96.56	74.30	89.36
SPI_HOST	220	220	100.00	92.95	91.30	90.76	96.79	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	232	248	93.55	96.59	95.09	96.60	98.10	94.48	95.64	92.86	-	91.84	100.00
SRAM_CTRL/RET	232	248	93.55	92.14	81.75	96.60	98.08	92.19	93.78	88.23	-	78.32	66.67
SYSRST_CTRL	358	410	87.32	94.34	98.37	85.79	98.86	-	99.35	99.33	97.65	100.00	95.51
TL_AGENT	10	10	100.00	-	-	-	-	-	-	-	-	-	-
UART	440	453	97.13	96.93	92.64	99.30	98.85	-	99.48	98.14	98.25	74.67	-
USBDEV	1752	1780	98.43	97.50	96.85	98.37	97.29	-	98.78	98.22	95.31	97.03	94.92
XBAR_MAIN	450	450	100.00	99.31	99.17	100.00	98.77	-	100.00	100.00	97.30	99.37	-
XBAR_PERI	450	450	100.00	99.57	99.13	100.00	99.57	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim