TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday May 25 2025 00:06:37 UTC

GitHub Revision: 2a67071

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 886 920 96.30 97.64
AES/UNMASKED 1548 1602 96.63 97.40
AES/MASKED 1556 1602 97.13 98.43
AON_TIMER 315 315 100.00 100.00
CSRNG 1617 1630 99.20 97.72
EDN 1107 1130 97.96 96.10
ENTROPY_SRC 1707 2570 66.42 96.47
HMAC 821 821 100.00 91.67
I2C 1847 2042 90.45 88.05
KEYMGR 1057 1110 95.23 97.79
KMAC/MASKED 926 940 98.51 95.32
KMAC/UNMASKED 902 940 95.96 93.78
LC_CTRL/VOLATILE_UNLOCK_DISABLED 1003 1030 97.38 90.14
LC_CTRL/VOLATILE_UNLOCK_ENABLED 1007 1030 97.77 90.27
OTBN 566 585 96.75 99.08
PATTGEN 454 570 79.65 98.72
PRIM_ALERT 79 80 98.75 94.85
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
ROM_CTRL/32KB 262 266 98.50 99.67
ROM_CTRL/64KB 266 266 100.00 99.67
RV_DM/USE_JTAG_INTERFACE 386 483 79.92 76.37
RV_TIMER 350 350 100.00 100.00
SPI_HOST 840 840 100.00 96.26
SPI_DEVICE/1R1W 1129 1151 98.09 94.54
SPI_DEVICE/2P 1149 1151 99.83 95.17
SRAM_CTRL/MAIN 1166 1190 97.98 96.06
SRAM_CTRL/RET 1155 1190 97.06 96.06
SYSRST_CTRL 911 932 97.75 97.03
UART 1314 1320 99.55 97.77
USBDEV 3904 3965 98.46 97.34
GPIO 970 1020 95.10 98.85
ALERT_HANDLER 655 850 77.06 98.87
CLKMGR 955 960 99.48 97.07
FLASH_CTRL 1001 1281 78.14 95.08
OTP_CTRL 1168 1343 86.97 93.25
PWM 115 276 41.67 99.21
PWRMGR 1066 1070 99.63 98.02
RSTMGR_CNSTY_CHK 10 10 100.00 95.87
RSTMGR 620 620 100.00 99.48
XBAR_MAIN 900 900 100.00 99.18
XBAR_PERI 900 900 100.00 99.20
CHIP 2760 2955 93.40 95.72