TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 892 920 96.96 97.32
AES/UNMASKED 1540 1602 96.13 97.21
AES/MASKED 1553 1602 96.94 98.28
AON_TIMER 315 315 100.00 98.89
CSRNG 1617 1630 99.20 97.64
EDN 1102 1130 97.52 95.64
ENTROPY_SRC/RNG_4BITS 2558 2570 99.53 94.17
HMAC 821 821 100.00 98.75
I2C 1802 2042 88.25 84.25
KEYMGR 1085 1110 97.75 97.65
KMAC/MASKED 936 940 99.57 95.33
KMAC/UNMASKED 924 940 98.30 93.56
LC_CTRL/VOLATILE_UNLOCK_DISABLED 998 1030 96.89 89.96
LC_CTRL/VOLATILE_UNLOCK_ENABLED 1001 1030 97.18 90.20
OTBN 298 585 50.94 93.73
PATTGEN 453 570 79.47 98.53
PRIM_ALERT 96 100 96.00 94.85
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
ROM_CTRL/32KB 260 266 97.74 99.16
ROM_CTRL/64KB 261 266 98.12 98.31
RV_DM/USE_JTAG_INTERFACE 341 483 70.60 81.23
RV_TIMER 312 350 89.14 95.77
SPI_HOST 838 840 99.76 95.12
SPI_DEVICE/1R1W 1128 1151 98.00 92.61
SPI_DEVICE/2P 1150 1151 99.91 93.16
SRAM_CTRL/MAIN 1160 1190 97.48 95.66
SRAM_CTRL/RET 1170 1190 98.32 95.64
SYSRST_CTRL 903 932 96.89 97.25
UART 1253 1320 94.92 94.53
USBDEV 3910 3970 98.49 97.29
GPIO 970 1020 95.10 96.08
ALERT_HANDLER 775 850 91.18 98.83
CLKMGR 958 960 99.79 97.00
FLASH_CTRL 1010 1281 78.84 96.31
OTP_CTRL 1160 1343 86.37 87.77
PWM 115 276 41.67 99.10
PWRMGR 516 1070 48.22 95.36
RSTMGR_CNSTY_CHK 9 10 90.00 95.87
RSTMGR 620 620 100.00 99.27
XBAR_MAIN 900 900 100.00 99.03
XBAR_PERI 900 900 100.00 98.95
CHIP 2747 2956 92.93 89.60