TOP_EARLGREY_BATCH_SIM Simulation Results (Summary)

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Name Passing Total Pass Rate Coverage
TL_AGENT 50 50 100.00 --
ADC_CTRL 896 920 97.39 97.37
AES/UNMASKED 1546 1602 96.50 97.14
AES/MASKED 1564 1602 97.63 98.36
AON_TIMER 315 315 100.00 98.89
CSRNG 1617 1630 99.20 97.57
EDN 1105 1130 97.79 95.52
ENTROPY_SRC/RNG_4BITS 2555 2570 99.42 94.12
HMAC 821 821 100.00 98.76
I2C 1809 2042 88.59 84.00
KEYMGR 1082 1110 97.48 97.64
KMAC/MASKED 935 940 99.47 94.93
KMAC/UNMASKED 931 940 99.04 93.65
LC_CTRL/VOLATILE_UNLOCK_DISABLED 831 1030 80.68 89.54
LC_CTRL/VOLATILE_UNLOCK_ENABLED 844 1030 81.94 89.93
OTBN 297 585 50.77 93.95
PATTGEN 449 570 78.77 98.53
PRIM_ALERT 98 100 98.00 94.85
PRIM_ESC 20 20 100.00 92.29
PRIM_LFSR 200 200 100.00 98.31
PRIM_PRESENT 50 50 100.00 93.41
PRIM_PRINCE 500 500 100.00 100.00
ROM_CTRL/32KB 257 266 96.62 99.14
ROM_CTRL/64KB 263 266 98.87 99.14
RV_DM/USE_JTAG_INTERFACE 346 483 71.64 81.35
RV_TIMER 307 350 87.71 95.77
SPI_HOST 837 840 99.64 95.09
SPI_DEVICE/1R1W 1127 1151 97.91 92.61
SPI_DEVICE/2P 1148 1151 99.74 93.16
SRAM_CTRL/MAIN 1162 1190 97.65 95.64
SRAM_CTRL/RET 1158 1190 97.31 95.64
SYSRST_CTRL 904 932 97.00 97.86
UART 1247 1320 94.47 94.52
USBDEV 3910 3970 98.49 97.31
GPIO 970 1020 95.10 96.08
ALERT_HANDLER 777 850 91.41 98.86
CLKMGR 953 960 99.27 96.93
FLASH_CTRL 999 1281 77.99 96.09
OTP_CTRL 1147 1343 85.41 87.64
PWM 115 276 41.67 99.11
PWRMGR 970 1070 90.65 95.32
RSTMGR_CNSTY_CHK 10 10 100.00 95.87
RSTMGR 620 620 100.00 99.27
XBAR_MAIN 900 900 100.00 99.07
XBAR_PERI 900 900 100.00 98.94
CHIP 2727 2956 92.25 89.67