Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	25	25	100.00	70.41	96.81	17.81	96.60	-	99.02	98.45	94.67	100.00	91.89
AES/MASKED	29	32	90.62	88.56	94.21	73.23	98.23	94.35	95.93	87.35	-	97.99	95.56
AES/UNMASKED	29	32	90.62	87.23	89.56	74.19	97.92	90.02	92.53	81.07	-	97.99	86.67
ALERT_HANDLER	25	26	96.15	91.31	92.51	82.90	98.52	-	99.76	98.76	93.36	90.00	80.65
AON_TIMER	23	23	100.00	96.69	99.17	94.23	96.67	-	99.09	98.56	99.05	100.00	-
CHIP	249	308	80.84	71.87	75.79	43.33	96.49	-	93.69	93.14	88.86	69.91	33.33
CLKMGR	24	27	88.89	91.27	97.16	83.70	92.94	-	98.62	98.02	89.96	99.19	100.00
CSRNG	18	19	94.74	87.16	92.19	75.62	93.67	96.82	97.66	92.09	-	93.31	85.71
EDN/EDN0	21	21	100.00	86.56	82.10	79.96	97.61	-	97.77	92.33	87.46	81.35	51.61
EDN/EDN1	21	21	100.00	87.59	83.92	80.67	98.18	-	98.18	93.51	90.15	95.70	42.05
ENTROPY_SRC/RNG_4BITS	21	23	91.30	76.11	88.25	55.66	84.40	94.25	96.94	86.36	-	75.97	93.75
GPIO	25	27	92.59	97.60	94.08	99.99	98.73	-	99.76	99.80	98.41	78.35	-
HMAC	28	28	100.00	76.07	86.71	43.91	97.60	-	99.54	98.54	95.18	46.17	94.12
I2C	44	50	88.00	86.56	79.02	84.46	96.19	-	96.63	92.90	87.49	74.04	44.05
KEYMGR_DPE/EARLGREY	12	14	85.71	65.19	82.67	15.22	97.67	-	97.60	93.77	86.84	59.47	75.68
KMAC/MASKED	29	40	72.50	80.33	65.71	81.19	94.09	-	97.12	89.96	83.65	23.02	34.81
KMAC/UNMASKED	29	40	72.50	79.49	63.96	80.20	94.31	-	95.53	88.51	83.62	21.49	30.66
LC_CTRL/VOLATILE_UNLOCK_DISABLED	38	39	97.44	90.21	84.01	91.94	94.69	-	97.15	93.61	79.45	86.29	63.55
LC_CTRL/VOLATILE_UNLOCK_ENABLED	38	39	97.44	90.47	84.12	92.47	94.83	-	97.17	93.71	79.56	87.53	62.62
OTBN	40	42	95.24	91.46	86.25	97.88	90.26	99.27	99.46	94.71	-	84.65	66.20
OTP_CTRL	27	30	90.00	80.47	76.70	70.14	94.57	-	88.60	83.13	89.98	78.20	43.58
PRIM_ALERT	4	5	80.00	90.05	94.05	-	86.05	-	100.00	95.83	95.83	100.00	78.57
PRIM_ESC	1	1	100.00	83.19	81.19	-	85.19	-	88.07	75.56	78.05	100.00	64.29
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	89.63	79.26	-	100.00	-	90.41	75.00	75.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	19	29	65.52	95.35	92.79	95.88	97.39	-	98.84	95.62	93.49	90.02	86.00
ROM_CTRL/192KB	18	19	94.74	94.30	92.46	93.05	97.39	-	98.68	97.83	97.92	94.56	73.33
RSTMGR	19	19	100.00	97.49	99.28	94.53	98.66	-	99.51	99.83	98.54	99.25	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.81	95.61	-	100.00	-	98.46	98.39	88.89	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	50	53	94.34	75.30	85.37	44.74	95.79	-	95.36	88.41	88.89	68.48	85.71
RV_TIMER	18	19	94.74	94.17	94.66	89.12	98.73	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	31	33	93.94	81.35	91.26	57.39	95.40	-	98.84	98.09	95.71	74.30	89.36
SPI_HOST	26	26	100.00	91.34	91.30	87.82	94.90	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	29	31	93.55	95.64	94.83	94.00	98.10	94.14	95.27	92.21	-	91.84	100.00
SRAM_CTRL/RET	29	31	93.55	91.34	81.75	94.20	98.08	92.19	93.78	88.23	-	78.32	66.67
SYSRST_CTRL	26	27	96.30	80.72	91.41	59.65	91.09	-	96.61	96.81	93.77	100.00	69.87
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	26	27	96.30	83.46	91.51	61.76	97.12	-	99.17	97.44	94.75	74.67	-
USBDEV	96	100	96.00	87.73	93.73	72.35	97.11	-	98.60	97.92	94.40	96.39	81.36
XBAR_MAIN	18	18	100.00	86.10	99.09	61.21	97.99	-	100.00	100.00	96.97	99.37	-
XBAR_PERI	18	18	100.00	75.67	99.13	29.76	98.13	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim