Simulation Results: top_earlgrey_batch_sim

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e JSON Branch: master
Block Tests Coverage Summary Code Coverage
Pass Total % Overall Code Functional Assertion Block Line Branch Condition Toggle FSM
ADC_CTRL
24 25 96.00 70.53 96.78 18.39 96.43 - 99.05 98.45 94.50 100.00 91.89
AES/MASKED
29 32 90.62 88.17 93.63 72.66 98.23 94.31 95.94 87.26 - 97.99 93.33
AES/UNMASKED
29 32 90.62 88.02 89.66 76.67 97.73 89.40 91.82 79.95 - 97.99 88.89
ALERT_HANDLER
25 26 96.15 88.98 89.37 79.70 97.87 - 99.65 98.27 91.89 86.08 70.97
AON_TIMER
23 23 100.00 96.46 99.14 92.13 98.10 - 99.09 98.56 99.05 99.88 -
CHIP
252 308 81.82 70.31 76.03 38.03 96.86 - 93.70 93.23 90.05 69.86 33.33
CLKMGR
27 27 100.00 93.43 98.61 86.62 95.06 - 99.24 99.06 95.06 99.68 100.00
CSRNG
18 19 94.74 88.52 92.28 79.18 94.10 96.90 97.74 92.30 - 93.37 85.71
EDN/EDN0
21 21 100.00 85.39 80.12 79.96 96.10 - 97.23 90.52 86.59 77.34 48.92
EDN/EDN1
20 21 95.24 86.98 82.10 80.67 98.18 - 97.88 92.64 90.15 87.80 42.05
ENTROPY_SRC/RNG_4BITS
22 23 95.65 75.49 88.40 53.17 84.89 94.45 97.16 86.58 - 76.10 93.75
GPIO
25 27 92.59 97.44 94.22 100.00 98.10 - 99.76 99.80 98.70 78.64 -
HMAC
28 28 100.00 75.77 86.61 43.32 97.38 - 99.49 98.37 94.90 46.17 94.12
I2C
44 50 88.00 85.64 79.13 80.34 97.46 - 96.82 92.83 85.68 73.87 46.43
KEYMGR_DPE/EARLGREY
12 14 85.71 65.09 82.50 15.09 97.67 - 97.52 93.58 86.46 59.24 75.68
KMAC/MASKED
29 40 72.50 79.88 65.62 80.06 93.95 - 97.05 89.71 83.45 23.06 34.81
KMAC/UNMASKED
29 40 72.50 79.47 63.90 80.20 94.31 - 95.53 88.51 83.33 21.49 30.66
LC_CTRL/VOLATILE_UNLOCK_DISABLED
39 39 100.00 90.88 84.40 93.55 94.69 - 97.24 93.90 79.45 87.85 63.55
LC_CTRL/VOLATILE_UNLOCK_ENABLED
36 39 92.31 89.30 81.86 91.22 94.83 - 96.95 93.00 78.66 78.08 62.62
OTBN
42 45 93.33 89.55 81.86 97.03 89.76 97.72 97.95 81.69 - 81.58 66.20
OTP_CTRL
23 30 76.67 78.70 75.28 68.47 92.34 - 88.17 81.58 89.24 77.33 40.10
PRIM_ALERT
4 5 80.00 90.61 95.18 - 86.05 - 100.00 95.83 97.92 100.00 82.14
PRIM_ESC
1 1 100.00 85.72 86.24 - 85.19 - 90.83 80.00 85.37 100.00 75.00
PRIM_LFSR
4 4 100.00 97.07 99.14 - 95.00 - 100.00 100.00 96.55 100.00 -
PRIM_PRESENT
1 1 100.00 89.63 79.26 - 100.00 - 90.41 75.00 75.00 76.63 -
PRIM_PRINCE
1 1 100.00 100.00 100.00 - 100.00 - 100.00 100.00 100.00 100.00 -
PWRMGR
24 29 82.76 94.73 90.07 96.21 97.91 - 98.93 95.62 93.78 90.02 72.00
ROM_CTRL/192KB
16 19 84.21 88.00 87.72 78.90 97.39 - 97.76 97.83 94.96 94.73 53.33
RSTMGR
19 19 100.00 98.09 99.25 96.77 98.26 - 99.51 99.83 98.26 99.41 -
RSTMGR_CNSTY_CHK
1 1 100.00 97.81 95.61 - 100.00 - 98.46 98.39 88.89 100.00 92.31
RV_DM/USE_JTAG_INTERFACE
49 53 92.45 82.88 83.62 69.24 95.79 - 94.46 86.26 87.08 68.48 81.82
RV_TIMER
17 19 89.47 96.50 94.66 97.06 97.77 - 100.00 100.00 100.00 78.66 -
SPI_DEVICE/1R1W
31 33 93.94 85.43 91.36 69.54 95.40 - 98.88 98.18 96.10 74.30 89.36
SPI_HOST
26 26 100.00 91.23 91.30 88.24 94.14 96.96 98.76 93.35 - 73.07 100.00
SRAM_CTRL/MAIN
29 31 93.55 95.25 94.32 93.60 97.83 93.47 94.53 90.91 - 91.84 100.00
SRAM_CTRL/RET
29 31 93.55 90.74 81.75 93.20 97.26 92.19 93.78 88.23 - 78.32 66.67
SYSRST_CTRL
27 27 100.00 84.32 92.66 65.79 94.51 - 97.26 97.40 95.13 99.77 73.72
TL_AGENT
1 1 100.00 - - - - - - - - - -
UART
26 27 96.30 83.17 91.68 59.57 98.27 - 99.17 97.44 95.45 74.67 -
USBDEV
96 100 96.00 88.87 93.44 75.88 97.29 - 98.62 97.96 94.03 96.92 79.66
XBAR_MAIN
18 18 100.00 88.01 99.10 66.44 98.48 - 100.00 100.00 97.03 99.37 -
XBAR_PERI
18 18 100.00 75.23 99.13 28.04 98.51 - 100.00 100.00 96.51 100.00 -