Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	134	233	57.51	67.28	95.57	13.74	92.54	-	98.80	97.28	87.43	99.76	94.59
AES/MASKED	1007	1110	90.72	97.54	96.54	97.71	98.38	96.87	97.77	92.61	-	97.99	97.78
AES/UNMASKED	993	1110	89.46	95.64	92.82	96.18	97.92	94.01	95.22	87.69	-	97.99	90.37
ALERT_HANDLER	530	593	89.38	99.07	98.83	99.51	98.88	-	99.99	99.99	97.55	96.62	100.00
AON_TIMER	180	180	100.00	98.77	98.69	100.00	97.62	-	99.09	98.56	99.05	98.04	-
CHIP	1757	2005	87.63	93.35	82.81	99.38	97.87	-	94.47	94.48	92.91	75.07	57.14
CLKMGR	242	273	88.64	94.29	98.85	87.82	96.19	-	99.28	99.06	95.93	100.00	100.00
CSRNG	1358	1403	96.79	94.62	96.20	90.50	97.16	98.53	99.54	96.38	-	93.64	95.24
EDN/EDN0	671	688	97.53	95.85	95.76	92.86	98.92	-	98.91	96.51	93.85	97.07	92.47
EDN/EDN1	674	688	97.97	95.61	95.95	92.44	98.44	-	98.48	94.59	95.08	96.15	95.45
ENTROPY_SRC/RNG_4BITS	2401	2453	97.88	91.03	90.43	92.68	89.98	95.16	97.82	88.01	-	79.01	96.88
FLASH_CTRL	1141	1154	98.87	96.92	95.34	98.39	97.02	-	96.09	97.40	94.76	96.60	91.84
GPIO	230	253	90.91	98.64	98.14	100.00	97.78	-	99.76	99.80	99.57	93.43	-
HMAC	694	694	100.00	98.61	98.61	99.62	97.60	-	99.74	99.67	96.57	100.00	97.06
I2C	584	755	77.35	90.05	83.36	89.11	97.67	-	97.25	93.83	89.25	88.84	47.62
KEYMGR	644	653	98.62	95.89	98.86	91.10	97.72	-	99.20	99.18	98.24	97.68	100.00
KMAC/MASKED	299	540	55.37	82.33	67.34	85.15	94.51	-	97.62	91.48	87.08	23.17	37.34
KMAC/UNMASKED	289	540	53.52	80.05	64.23	81.48	94.45	-	95.49	88.58	84.89	21.54	30.66
LC_CTRL/VOLATILE_UNLOCK_DISABLED	514	523	98.28	92.18	85.93	96.06	94.55	-	97.28	94.00	81.84	88.33	68.22
LC_CTRL/VOLATILE_UNLOCK_ENABLED	518	523	99.04	92.20	86.02	95.88	94.69	-	97.26	93.95	81.41	88.33	69.16
OTBN	421	436	96.56	93.25	82.81	100.00	96.94	97.85	98.03	82.61	-	83.00	67.61
OTP_CTRL	785	903	86.93	91.12	85.44	92.45	95.47	-	90.16	86.66	94.00	92.68	63.72
PRIM_ALERT	58	60	96.67	91.33	96.61	-	86.05	-	100.00	95.83	97.92	100.00	89.29
PRIM_ESC	20	20	100.00	89.45	93.71	-	85.19	-	95.41	88.89	87.80	100.00	96.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	10	10	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	261	273	95.60	98.51	97.57	99.01	98.96	-	99.09	96.37	96.75	99.62	96.00
ROM_CTRL/32KB	0	156	0.00	-	-	-	-	-	-	-	-	-	-
ROM_CTRL/64KB	0	156	0.00	-	-	-	-	-	-	-	-	-	-
RSTMGR	148	148	100.00	99.12	99.66	98.76	98.93	-	99.51	99.83	99.31	100.00	-
RSTMGR_CNSTY_CHK	8	10	80.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	331	368	89.95	85.46	88.40	72.20	95.79	-	96.25	90.50	90.28	71.45	93.51
RV_TIMER	186	223	83.41	97.40	94.66	98.82	98.73	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	394	416	94.71	96.15	94.19	98.86	95.40	-	98.89	98.28	96.55	87.85	89.36
SPI_HOST	218	220	99.09	92.44	91.30	90.76	95.27	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	224	248	90.32	96.83	95.81	96.60	98.10	96.23	96.90	94.48	-	91.84	100.00
SRAM_CTRL/RET	223	248	89.92	92.78	83.45	96.80	98.08	93.95	95.06	89.80	-	82.29	66.67
SYSRST_CTRL	406	410	99.02	96.60	98.28	92.78	98.75	-	99.42	99.52	97.58	100.00	94.87
TL_AGENT	10	10	100.00	-	-	-	-	-	-	-	-	-	-
UART	439	453	96.91	98.33	96.86	99.30	98.85	-	99.48	98.14	98.25	91.55	-
USBDEV	1755	1780	98.60	97.56	96.93	98.46	97.29	-	98.79	98.34	95.55	97.03	94.92
XBAR_MAIN	450	450	100.00	99.32	99.10	100.00	98.87	-	100.00	100.00	96.76	99.65	-
XBAR_PERI	450	450	100.00	99.53	99.13	100.00	99.46	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim