Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	15	25	60.00	65.76	92.25	13.12	91.90	-	98.00	96.23	86.19	99.76	81.08
AES/MASKED	28	32	87.50	87.92	93.60	72.08	98.09	94.27	95.96	87.11	-	97.99	93.33
AES/UNMASKED	30	32	93.75	87.22	89.73	74.19	97.73	89.71	91.95	80.10	-	97.99	88.89
ALERT_HANDLER	25	26	96.15	90.73	92.29	81.68	98.21	-	99.73	98.72	92.94	89.39	80.65
AON_TIMER	23	23	100.00	94.99	98.68	88.19	98.10	-	99.09	98.56	98.93	98.13	-
CHIP	251	328	76.52	74.55	83.67	42.50	97.49	-	94.00	92.34	87.68	87.20	57.14
CLKMGR	25	27	92.59	91.05	96.68	82.68	93.79	-	96.83	96.91	90.79	98.87	100.00
CSRNG	16	19	84.21	86.30	92.34	72.45	94.10	97.05	97.73	92.68	-	93.24	85.71
EDN/EDN0	20	21	95.24	84.37	78.24	78.77	96.10	-	96.85	89.26	83.63	74.71	46.77
EDN/EDN1	21	21	100.00	87.07	82.14	80.88	98.18	-	97.72	92.42	89.69	87.68	43.18
ENTROPY_SRC/RNG_4BITS	21	23	91.30	76.37	89.02	55.36	84.73	94.47	97.19	86.75	-	76.31	95.83
FLASH_CTRL	78	79	98.73	95.75	94.32	95.91	97.02	-	95.95	97.16	93.68	97.74	87.07
GPIO	25	27	92.59	97.59	94.05	99.99	98.73	-	99.76	99.80	98.70	77.92	-
HMAC	28	28	100.00	79.12	97.21	42.78	97.38	-	99.74	99.17	95.96	100.00	91.18
I2C	44	50	88.00	84.56	78.32	79.39	95.98	-	96.45	92.41	85.16	72.95	44.64
KEYMGR	29	30	96.67	82.48	92.72	57.24	97.49	-	98.68	97.44	93.24	90.53	83.72
KMAC/MASKED	31	40	77.50	80.91	69.63	77.18	95.92	-	95.49	90.06	86.72	29.04	46.84
KMAC/UNMASKED	31	40	77.50	80.99	67.62	77.99	97.37	-	94.10	88.66	86.33	27.41	41.61
LC_CTRL/VOLATILE_UNLOCK_DISABLED	39	39	100.00	90.28	83.88	92.70	94.27	-	97.15	93.56	79.79	87.24	61.68
LC_CTRL/VOLATILE_UNLOCK_ENABLED	39	39	100.00	91.05	84.23	93.95	94.97	-	97.13	93.37	79.34	86.83	64.49
OTBN	42	42	100.00	89.94	81.90	97.88	90.04	97.75	97.94	82.06	-	81.40	66.20
OTP_CTRL	28	30	93.33	82.89	78.49	75.67	94.50	-	88.64	83.26	90.05	87.10	43.40
PRIM_ALERT	5	5	100.00	90.76	95.47	-	86.05	-	100.00	95.83	95.83	100.00	85.71
PRIM_ESC	1	1	100.00	86.36	87.54	-	85.19	-	92.66	82.22	87.80	100.00	75.00
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	28	29	96.55	97.61	95.79	98.35	98.69	-	99.09	96.37	96.32	91.15	96.00
ROM_CTRL/32KB	18	19	94.74	96.46	95.42	96.42	97.53	-	99.19	98.54	97.18	95.54	86.67
ROM_CTRL/64KB	18	19	94.74	96.54	95.48	96.90	97.24	-	99.33	99.27	97.47	94.64	86.67
RSTMGR	19	19	100.00	96.51	99.32	91.29	98.93	-	99.51	99.83	98.54	99.41	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	52	53	98.11	77.09	85.38	50.18	95.71	-	94.99	89.17	88.33	71.29	83.12
RV_TIMER	16	19	84.21	95.92	94.66	95.00	98.09	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	31	33	93.94	84.05	90.27	66.47	95.40	-	98.81	98.07	95.54	69.55	89.36
SPI_HOST	26	26	100.00	92.46	91.30	89.50	96.60	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	28	31	90.32	96.22	95.69	95.00	97.96	96.03	96.75	94.17	-	91.84	100.00
SRAM_CTRL/RET	28	31	90.32	90.15	82.32	90.60	97.53	93.76	94.99	89.36	-	78.27	66.67
SYSRST_CTRL	27	27	100.00	84.22	93.65	63.21	95.79	-	97.86	97.74	95.33	99.77	77.56
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	26	27	96.30	81.05	91.61	52.97	98.56	-	99.17	97.44	95.33	74.49	-
USBDEV	98	100	98.00	88.76	94.46	74.52	97.29	-	98.72	98.21	93.60	97.02	84.75
XBAR_MAIN	18	18	100.00	79.20	99.11	40.50	97.98	-	100.00	100.00	96.42	100.00	-
XBAR_PERI	18	18	100.00	80.83	99.13	45.22	98.14	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim