Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	15	25	60.00	66.28	93.74	12.89	92.22	-	98.86	97.40	86.89	99.05	86.49
AES/MASKED	30	32	93.75	89.39	93.51	76.29	98.38	94.15	95.85	86.88	-	97.99	93.33
AES/UNMASKED	29	32	90.62	87.19	89.09	74.76	97.73	89.44	91.95	79.76	-	97.99	86.67
ALERT_HANDLER	24	26	92.31	90.31	90.68	82.13	98.12	-	99.64	98.64	91.36	91.20	72.58
AON_TIMER	23	23	100.00	96.12	99.05	92.65	96.67	-	99.09	98.56	99.05	99.50	-
CHIP	243	328	74.09	74.68	83.73	42.81	97.49	-	94.11	92.41	88.35	86.62	57.14
CLKMGR	26	27	96.30	92.66	98.06	84.73	95.20	-	98.97	98.43	93.69	99.19	100.00
CSRNG	17	19	89.47	88.07	92.18	77.49	94.54	96.82	97.55	92.09	-	93.37	85.71
EDN/EDN0	21	21	100.00	83.58	77.62	78.77	94.36	-	96.52	88.42	84.45	73.54	45.16
EDN/EDN1	21	21	100.00	86.67	82.41	80.46	97.14	-	98.18	93.29	89.54	86.71	44.32
ENTROPY_SRC/RNG_4BITS	21	23	91.30	73.47	86.09	51.06	83.25	94.17	96.89	85.87	-	76.20	85.42
FLASH_CTRL	79	79	100.00	95.48	93.95	95.73	96.77	-	95.96	97.12	93.80	95.82	87.07
GPIO	26	27	96.30	97.71	94.41	100.00	98.73	-	99.76	99.80	97.98	80.09	-
HMAC	28	28	100.00	79.70	97.80	43.69	97.60	-	99.74	99.17	95.96	100.00	94.12
I2C	44	50	88.00	86.11	78.85	82.24	97.25	-	96.60	92.69	87.41	73.52	44.05
KEYMGR	30	30	100.00	85.95	95.51	64.86	97.49	-	98.76	97.72	93.84	96.53	90.70
KMAC/MASKED	30	40	75.00	80.52	68.73	76.21	96.62	-	95.45	89.38	84.09	29.14	45.57
KMAC/UNMASKED	31	40	77.50	80.33	67.32	76.60	97.08	-	93.89	88.43	85.30	27.39	41.61
LC_CTRL/VOLATILE_UNLOCK_DISABLED	39	39	100.00	91.15	84.36	94.13	94.97	-	97.15	93.56	79.86	86.73	64.49
LC_CTRL/VOLATILE_UNLOCK_ENABLED	38	39	97.44	90.71	83.80	93.77	94.55	-	97.04	93.37	79.13	86.85	62.62
OTBN	39	42	92.86	89.74	81.92	97.46	89.84	97.75	97.94	81.85	-	81.69	66.20
OTP_CTRL	27	30	90.00	82.25	79.01	75.09	92.65	-	88.40	82.18	90.05	88.39	46.01
PRIM_ALERT	5	5	100.00	90.97	95.89	-	86.05	-	100.00	95.83	97.92	100.00	85.71
PRIM_ESC	1	1	100.00	83.19	81.19	-	85.19	-	88.07	75.56	78.05	100.00	64.29
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	27	29	93.10	98.11	97.34	98.02	98.96	-	99.09	96.37	95.62	99.62	96.00
ROM_CTRL/32KB	18	19	94.74	97.77	98.52	97.85	96.95	-	99.46	99.64	98.66	94.85	100.00
ROM_CTRL/64KB	18	19	94.74	97.02	96.83	97.14	97.10	-	99.33	98.91	97.62	94.97	93.33
RSTMGR	19	19	100.00	98.53	99.31	97.76	98.53	-	99.51	99.83	98.75	99.16	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	51	53	96.23	76.13	84.46	48.23	95.71	-	94.99	88.83	88.75	67.93	81.82
RV_TIMER	16	19	84.21	97.62	100.00	94.12	98.73	-	100.00	100.00	100.00	100.00	-
SPI_DEVICE/1R1W	31	33	93.94	83.52	91.27	63.89	95.40	-	98.87	98.16	96.13	73.83	89.36
SPI_HOST	26	26	100.00	91.87	91.30	88.66	95.65	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	28	31	90.32	96.05	96.46	94.40	97.28	95.63	96.38	93.37	-	96.09	100.00
SRAM_CTRL/RET	28	31	90.32	91.38	82.31	94.57	97.26	93.69	94.91	89.36	-	78.28	66.67
SYSRST_CTRL	27	27	100.00	85.22	92.46	70.97	92.24	-	96.91	97.14	94.54	100.00	73.72
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	26	27	96.30	86.29	96.59	63.73	98.56	-	99.48	98.14	97.20	91.55	-
USBDEV	97	100	97.00	89.10	94.41	75.61	97.29	-	98.70	98.13	93.67	96.82	84.75
XBAR_MAIN	18	18	100.00	85.26	99.13	58.65	98.01	-	100.00	100.00	96.52	100.00	-
XBAR_PERI	18	18	100.00	73.69	99.13	23.70	98.24	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim