Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	15	25	60.00	66.40	93.84	12.99	92.38	-	98.74	97.22	86.97	99.76	86.49
AES/MASKED	28	32	87.50	89.30	94.73	74.95	98.23	95.14	96.05	89.33	-	97.99	95.56
AES/UNMASKED	28	32	87.50	87.32	89.66	74.57	97.73	89.59	91.93	79.84	-	97.99	88.89
ALERT_HANDLER	24	26	92.31	88.95	91.11	77.53	98.22	-	99.66	98.22	91.60	91.88	74.19
AON_TIMER	23	23	100.00	96.36	98.71	93.70	96.67	-	99.09	98.56	98.69	98.51	-
CHIP	242	328	73.78	75.93	81.62	48.79	97.37	-	94.16	93.64	89.58	73.57	57.14
CLKMGR	26	27	96.30	92.71	97.99	85.93	94.21	-	99.09	98.85	92.03	100.00	100.00
CSRNG	16	19	84.21	87.90	92.23	77.37	94.10	96.99	97.62	92.51	-	93.10	85.71
EDN/EDN0	21	21	100.00	87.78	84.30	82.74	96.31	-	97.99	93.17	86.54	86.82	56.99
EDN/EDN1	21	21	100.00	87.20	83.71	79.20	98.70	-	98.18	93.51	88.62	95.06	43.18
ENTROPY_SRC/RNG_4BITS	21	23	91.30	75.65	88.45	53.77	84.73	94.43	97.11	86.58	-	76.38	93.75
FLASH_CTRL	77	79	97.47	95.64	93.92	96.16	96.85	-	95.95	97.16	93.37	96.07	87.07
GPIO	26	27	96.30	97.00	94.16	100.00	96.84	-	99.76	99.80	97.69	79.37	-
HMAC	28	28	100.00	78.90	97.07	42.03	97.60	-	99.64	98.84	95.67	100.00	91.18
I2C	42	50	84.00	85.19	78.19	79.92	97.46	-	96.38	92.19	84.63	73.69	44.05
KEYMGR	30	30	100.00	83.40	94.51	58.19	97.49	-	98.64	97.72	94.12	96.04	86.05
KMAC/MASKED	30	40	75.00	80.29	66.16	80.34	94.37	-	97.32	90.49	83.86	23.06	36.08
KMAC/UNMASKED	27	40	67.50	77.70	63.60	75.93	93.58	-	95.27	87.66	82.92	21.49	30.66
LC_CTRL/VOLATILE_UNLOCK_DISABLED	39	39	100.00	90.46	83.70	93.55	94.13	-	97.20	93.70	79.43	85.53	62.62
LC_CTRL/VOLATILE_UNLOCK_ENABLED	38	39	97.44	90.59	83.62	93.19	94.97	-	97.17	93.66	79.61	83.16	64.49
OTBN	41	42	97.62	91.27	86.25	97.46	90.10	99.28	99.47	94.82	-	84.53	66.20
OTP_CTRL	28	30	93.33	81.09	76.53	72.11	94.64	-	88.53	83.55	90.21	76.10	44.27
PRIM_ALERT	4	5	80.00	89.48	92.92	-	86.05	-	100.00	95.83	93.75	100.00	75.00
PRIM_ESC	1	1	100.00	86.72	88.25	-	85.19	-	92.66	82.22	87.80	100.00	78.57
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	28	29	96.55	98.03	97.48	98.19	98.43	-	99.09	96.37	96.32	99.62	96.00
ROM_CTRL/32KB	0	19	0.00	-	-	-	-	-	-	-	-	-	-
ROM_CTRL/64KB	0	19	0.00	-	-	-	-	-	-	-	-	-	-
RSTMGR	19	19	100.00	98.83	99.19	98.51	98.80	-	99.51	99.83	98.19	99.25	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	51	53	96.23	77.82	85.90	51.78	95.79	-	95.20	88.50	88.19	74.47	83.12
RV_TIMER	16	19	84.21	95.98	94.66	96.47	96.82	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	29	33	87.88	83.86	93.68	62.50	95.40	-	98.83	98.07	95.41	86.74	89.36
SPI_HOST	26	26	100.00	93.13	95.03	89.08	95.27	96.96	98.76	93.35	-	88.02	100.00
SRAM_CTRL/MAIN	28	31	90.32	95.36	95.75	93.20	97.14	96.16	96.82	94.32	-	91.84	100.00
SRAM_CTRL/RET	28	31	90.32	91.48	82.11	94.40	97.94	93.47	94.61	88.85	-	78.32	66.67
SYSRST_CTRL	27	27	100.00	85.50	92.82	69.43	94.25	-	97.28	97.29	95.18	100.00	74.36
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	27	27	100.00	80.56	91.22	51.89	98.56	-	99.17	96.97	94.63	74.12	-
USBDEV	97	100	97.00	88.16	94.83	72.35	97.29	-	98.68	98.17	94.37	96.50	86.44
XBAR_MAIN	18	18	100.00	89.00	99.07	70.05	97.88	-	100.00	100.00	96.64	99.65	-
XBAR_PERI	18	18	100.00	80.81	99.13	45.19	98.12	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim