Simulation Results: top_earlgrey_batch_sim

 
17/08/2026 15:30:35 DVSim: v1.50.1 sha: b9d39c6 JSON Branch: master
Block Tests Coverage Summary Code Coverage
Pass Total % Overall Code Functional Assertion Block Line Branch Condition Toggle FSM
ADC_CTRL
25 25 100.00 70.62 96.82 18.44 96.60 - 99.02 98.39 94.79 100.00 91.89
AES/MASKED
29 32 90.62 89.93 93.56 78.01 98.23 94.21 95.91 87.01 - 97.99 93.33
AES/UNMASKED
29 32 90.62 86.38 89.13 72.28 97.73 89.50 91.86 79.99 - 97.99 86.67
ALERT_HANDLER
23 26 88.46 88.52 91.54 75.76 98.27 - 99.69 97.74 91.51 91.32 77.42
AON_TIMER
23 23 100.00 96.58 99.17 93.18 97.39 - 99.09 98.56 99.05 100.00 -
CHIP
0 326 0.00 - - - - - - - - - -
CLKMGR
25 27 92.59 93.19 98.21 85.59 95.76 - 98.95 98.48 94.44 99.19 100.00
CSRNG
16 19 84.21 88.26 92.26 78.43 94.10 96.85 97.69 92.26 - 93.37 85.71
EDN/EDN0
21 21 100.00 84.27 78.62 78.97 95.23 - 96.79 88.56 83.75 72.41 51.61
EDN/EDN1
21 21 100.00 86.56 82.19 78.78 98.70 - 98.18 93.29 88.69 86.46 44.32
ENTROPY_SRC/RNG_4BITS
21 23 91.30 74.15 88.16 49.89 84.40 94.32 97.09 86.31 - 76.54 92.71
FLASH_CTRL
77 79 97.47 95.44 93.63 95.67 97.02 - 95.97 97.23 93.64 95.60 85.71
GPIO
25 27 92.59 97.48 94.01 100.00 98.42 - 99.76 99.80 98.70 77.78 -
HMAC
28 28 100.00 79.31 97.65 42.89 97.38 - 99.64 98.84 95.67 100.00 94.12
I2C
45 50 90.00 85.24 78.99 79.28 97.46 - 96.47 92.55 86.06 74.04 45.83
KEYMGR
30 30 100.00 85.21 95.31 62.83 97.49 - 98.88 98.08 93.36 95.54 90.70
KMAC/MASKED
29 40 72.50 79.65 66.64 78.22 94.09 - 96.96 89.91 85.83 23.15 37.34
KMAC/UNMASKED
29 40 72.50 78.05 63.64 76.07 94.45 - 95.21 87.89 82.88 21.54 30.66
LC_CTRL/VOLATILE_UNLOCK_DISABLED
38 39 97.44 90.67 83.99 93.19 94.83 - 97.20 93.70 79.08 86.44 63.55
LC_CTRL/VOLATILE_UNLOCK_ENABLED
39 39 100.00 90.68 84.39 92.83 94.83 - 97.26 93.80 79.41 86.99 64.49
OTBN
39 42 92.86 89.87 81.39 98.73 89.49 97.73 97.93 81.85 - 79.56 66.20
OTP_CTRL
27 30 90.00 81.55 78.51 71.82 94.32 - 88.60 83.69 90.32 84.09 45.83
PRIM_ALERT
5 5 100.00 90.76 95.47 - 86.05 - 100.00 95.83 95.83 100.00 85.71
PRIM_ESC
1 1 100.00 85.63 86.07 - 85.19 - 92.66 82.22 80.49 100.00 75.00
PRIM_LFSR
4 4 100.00 97.07 99.14 - 95.00 - 100.00 100.00 96.55 100.00 -
PRIM_PRESENT
1 1 100.00 95.88 91.76 - 100.00 - 90.41 100.00 100.00 76.63 -
PRIM_PRINCE
1 1 100.00 100.00 100.00 - 100.00 - 100.00 100.00 100.00 100.00 -
PWRMGR
27 29 93.10 97.67 97.40 97.69 97.91 - 99.09 96.37 95.90 99.62 96.00
ROM_CTRL/32KB
18 19 94.74 95.87 92.72 97.35 97.53 - 98.94 98.54 97.77 95.02 73.33
ROM_CTRL/64KB
18 19 94.74 95.26 91.29 97.11 97.39 - 98.81 98.18 97.62 95.19 66.67
RSTMGR
19 19 100.00 98.57 99.30 97.76 98.66 - 99.51 99.83 99.03 98.83 -
RSTMGR_CNSTY_CHK
1 1 100.00 97.52 95.05 - 100.00 - 98.41 98.31 86.21 100.00 92.31
RV_DM/USE_JTAG_INTERFACE
49 53 92.45 77.66 84.66 52.28 96.03 - 94.78 87.33 86.94 68.54 85.71
RV_TIMER
17 19 89.47 96.62 94.66 96.47 98.73 - 100.00 100.00 100.00 78.66 -
SPI_DEVICE/1R1W
31 33 93.94 84.77 91.39 67.51 95.40 - 98.86 98.21 96.22 74.30 89.36
SPI_HOST
26 26 100.00 91.74 91.30 88.66 95.27 96.96 98.76 93.35 - 73.07 100.00
SRAM_CTRL/MAIN
31 31 100.00 94.67 94.38 91.80 97.83 94.34 94.75 90.91 - 91.84 100.00
SRAM_CTRL/RET
31 31 100.00 91.55 81.65 95.20 97.81 92.87 93.86 87.76 - 78.32 66.67
SYSRST_CTRL
27 27 100.00 85.18 94.10 65.38 96.07 - 97.92 97.85 95.23 100.00 79.49
TL_AGENT
1 1 100.00 - - - - - - - - - -
UART
26 27 96.30 85.10 92.55 64.47 98.27 - 99.48 98.14 97.90 74.67 -
USBDEV
98 100 98.00 89.18 94.92 75.34 97.29 - 98.74 98.21 94.19 97.03 86.44
XBAR_MAIN
18 18 100.00 81.24 99.05 46.71 97.95 - 100.00 100.00 96.52 99.69 -
XBAR_PERI
18 18 100.00 79.39 99.09 40.78 98.31 - 100.00 100.00 96.38 100.00 -