Simulation Results: top_earlgrey_batch_sim

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 JSON Branch: master
Block Tests Coverage Summary Code Coverage
Pass Total % Overall Code Functional Assertion Block Line Branch Condition Toggle FSM
ADC_CTRL
25 25 100.00 70.71 96.79 18.74 96.60 - 99.05 98.51 94.50 100.00 91.89
AES/MASKED
28 32 87.50 88.87 94.59 73.80 98.23 94.86 95.82 88.99 - 97.99 95.56
AES/UNMASKED
28 32 87.50 86.74 89.63 72.85 97.73 89.40 91.72 79.91 - 97.99 88.89
ALERT_HANDLER
24 26 92.31 90.86 91.79 82.46 98.33 - 99.70 98.47 92.33 91.01 77.42
AON_TIMER
23 23 100.00 95.85 99.15 90.55 97.86 - 99.09 98.56 98.93 100.00 -
CHIP
249 308 80.84 70.18 75.82 37.98 96.74 - 93.72 93.23 88.57 70.24 33.33
CLKMGR
26 27 96.30 93.60 98.24 86.79 95.76 - 99.02 98.59 94.40 99.19 100.00
CSRNG
18 19 94.74 88.19 92.31 79.02 93.23 96.95 97.73 92.43 - 93.37 85.71
EDN/EDN0
21 21 100.00 85.93 80.29 80.75 96.75 - 97.23 90.79 86.42 78.08 48.92
EDN/EDN1
21 21 100.00 87.58 83.62 80.67 98.44 - 98.18 93.29 88.46 93.84 44.32
ENTROPY_SRC/RNG_4BITS
22 23 95.65 75.87 87.54 55.66 84.40 94.28 96.99 86.31 - 76.23 90.62
GPIO
25 27 92.59 96.94 93.97 100.00 96.84 - 99.76 99.80 98.27 78.07 -
HMAC
28 28 100.00 75.07 86.11 41.49 97.60 - 99.54 98.21 95.46 46.17 91.18
I2C
41 50 82.00 85.69 78.65 81.18 97.25 - 96.72 92.62 84.63 74.04 45.24
KEYMGR_DPE/EARLGREY
12 14 85.71 65.08 82.47 15.09 97.67 - 97.15 93.58 86.46 59.49 75.68
KMAC/MASKED
29 40 72.50 80.10 65.45 80.48 94.37 - 97.09 89.90 82.44 23.02 34.81
KMAC/UNMASKED
30 40 75.00 79.74 66.25 77.49 95.47 - 96.54 90.48 86.11 24.52 33.58
LC_CTRL/VOLATILE_UNLOCK_DISABLED
39 39 100.00 90.20 83.21 92.83 94.55 - 97.24 93.61 79.45 84.06 61.68
LC_CTRL/VOLATILE_UNLOCK_ENABLED
38 39 97.44 90.47 83.73 93.55 94.13 - 97.17 93.57 79.35 84.99 63.55
OTBN
40 42 95.24 91.48 86.16 98.31 89.96 99.22 99.44 94.43 - 84.55 66.20
OTP_CTRL
29 30 96.67 82.66 78.53 75.27 94.19 - 88.80 84.59 92.89 80.21 46.18
PRIM_ALERT
5 5 100.00 90.76 95.47 - 86.05 - 100.00 95.83 95.83 100.00 85.71
PRIM_ESC
1 1 100.00 82.83 80.48 - 85.19 - 88.07 75.56 78.05 100.00 60.71
PRIM_LFSR
4 4 100.00 97.07 99.14 - 95.00 - 100.00 100.00 96.55 100.00 -
PRIM_PRESENT
1 1 100.00 89.63 79.26 - 100.00 - 90.41 75.00 75.00 76.63 -
PRIM_PRINCE
1 1 100.00 100.00 100.00 - 100.00 - 100.00 100.00 100.00 100.00 -
PWRMGR
24 29 82.76 96.02 94.55 96.38 97.13 - 98.93 95.62 94.20 90.02 94.00
ROM_CTRL/192KB
18 19 94.74 96.57 95.70 97.36 96.66 - 99.21 99.28 98.37 94.95 86.67
RSTMGR
19 19 100.00 97.05 99.34 93.28 98.53 - 99.51 99.83 98.96 99.08 -
RSTMGR_CNSTY_CHK
1 1 100.00 97.81 95.61 - 100.00 - 98.46 98.39 88.89 100.00 92.31
RV_DM/USE_JTAG_INTERFACE
51 53 96.23 74.20 84.28 42.76 95.55 - 94.72 87.42 87.22 68.90 83.12
RV_TIMER
17 19 89.47 93.83 94.66 90.00 96.82 - 100.00 100.00 100.00 78.66 -
SPI_DEVICE/1R1W
31 33 93.94 89.25 91.24 81.10 95.40 - 98.88 98.20 95.64 74.14 89.36
SPI_HOST
26 26 100.00 91.54 91.30 88.24 95.09 96.96 98.76 93.35 - 73.07 100.00
SRAM_CTRL/MAIN
29 31 93.55 95.69 94.24 95.00 97.83 93.47 94.53 90.91 - 91.51 100.00
SRAM_CTRL/RET
29 31 93.55 90.24 81.75 91.15 97.81 92.19 93.78 88.23 - 78.32 66.67
SYSRST_CTRL
26 27 96.30 81.70 89.84 65.87 89.39 - 95.50 96.22 92.75 100.00 64.74
TL_AGENT
1 1 100.00 - - - - - - - - - -
UART
26 27 96.30 78.56 92.49 44.93 98.27 - 99.48 98.14 97.67 74.67 -
USBDEV
97 100 97.00 88.44 94.13 73.89 97.29 - 98.64 97.96 93.96 97.03 83.05
XBAR_MAIN
18 18 100.00 74.10 99.04 25.39 97.88 - 100.00 100.00 96.78 99.37 -
XBAR_PERI
18 18 100.00 75.01 99.13 27.76 98.13 - 100.00 100.00 96.51 100.00 -