Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	134	233	57.51	67.30	95.60	13.59	92.71	-	98.86	97.40	87.39	99.76	94.59
AES/MASKED	1003	1110	90.36	97.23	96.57	96.75	98.38	96.92	97.78	92.73	-	97.99	97.78
AES/UNMASKED	988	1110	89.01	95.95	92.98	96.75	98.11	93.96	95.19	87.62	-	97.99	91.11
ALERT_HANDLER	535	593	90.22	99.01	98.91	99.26	98.87	-	99.99	99.99	97.55	97.04	100.00
AON_TIMER	180	180	100.00	98.97	98.81	100.00	98.10	-	99.09	98.56	99.05	98.53	-
CHIP	1704	2005	84.99	93.50	83.06	99.44	97.99	-	94.84	94.75	93.15	75.43	57.14
CLKMGR	240	273	87.91	93.88	98.57	87.31	95.76	-	99.07	98.74	95.85	99.19	100.00
CSRNG	1355	1403	96.58	94.73	96.17	90.86	97.16	98.49	99.50	96.30	-	93.64	95.24
EDN/EDN0	680	688	98.84	95.84	95.95	92.66	98.92	-	98.91	96.51	94.20	97.12	93.01
EDN/EDN1	675	688	98.11	95.68	95.90	92.44	98.70	-	98.48	94.59	94.85	96.15	95.45
ENTROPY_SRC/RNG_4BITS	2392	2453	97.51	91.22	90.85	92.83	89.98	95.21	97.84	88.12	-	79.53	97.92
FLASH_CTRL	1141	1154	98.87	96.89	95.36	98.36	96.94	-	96.10	97.42	94.86	96.60	91.84
GPIO	230	253	90.91	98.96	98.14	100.00	98.73	-	99.76	99.80	99.57	93.43	-
HMAC	693	694	99.86	98.39	99.20	99.68	96.29	-	99.74	99.67	96.57	100.00	100.00
I2C	579	755	76.69	89.02	80.69	89.11	97.25	-	97.37	94.04	89.21	74.04	48.81
KEYMGR	646	653	98.93	95.71	98.36	91.05	97.72	-	99.16	99.09	98.20	97.68	97.67
KMAC/MASKED	290	540	53.70	82.68	70.21	82.46	95.36	-	98.00	92.65	88.99	29.00	42.41
KMAC/UNMASKED	284	540	52.59	80.88	65.71	82.19	94.74	-	95.85	89.81	85.59	21.54	35.77
LC_CTRL/VOLATILE_UNLOCK_DISABLED	513	523	98.09	92.21	85.69	96.24	94.69	-	97.28	93.85	81.70	88.33	67.29
LC_CTRL/VOLATILE_UNLOCK_ENABLED	519	523	99.24	92.35	86.15	96.06	94.83	-	97.26	94.09	81.89	88.33	69.16
OTBN	426	436	97.71	94.75	87.12	100.00	97.14	99.37	99.56	95.44	-	85.88	67.61
OTP_CTRL	790	903	87.49	91.18	85.56	92.52	95.47	-	90.31	86.89	94.08	92.64	63.89
PRIM_ALERT	57	60	95.00	91.33	96.61	-	86.05	-	100.00	95.83	97.92	100.00	89.29
PRIM_ESC	20	20	100.00	89.45	93.71	-	85.19	-	95.41	88.89	87.80	100.00	96.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	10	10	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	256	273	93.77	98.34	97.57	99.01	98.43	-	99.09	96.37	96.75	99.62	96.00
ROM_CTRL/32KB	0	156	0.00	-	-	-	-	-	-	-	-	-	-
ROM_CTRL/64KB	0	156	0.00	-	-	-	-	-	-	-	-	-	-
RSTMGR	148	148	100.00	99.03	99.66	98.51	98.93	-	99.51	99.83	99.31	100.00	-
RSTMGR_CNSTY_CHK	10	10	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	333	368	90.49	86.96	90.10	74.92	95.87	-	96.25	90.50	90.56	77.11	96.10
RV_TIMER	182	223	81.61	97.40	94.66	99.12	98.41	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	395	416	94.95	95.30	91.48	98.91	95.52	-	98.90	98.30	96.53	74.30	89.36
SPI_HOST	219	220	99.55	92.88	91.30	90.76	96.60	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	223	248	89.92	96.85	95.85	96.60	98.10	96.30	97.05	94.50	-	91.84	100.00
SRAM_CTRL/RET	224	248	90.32	92.46	82.51	96.80	98.08	94.03	95.21	89.83	-	78.32	66.67
SYSRST_CTRL	401	410	97.80	96.43	98.37	92.16	98.75	-	99.44	99.56	97.98	100.00	94.87
TL_AGENT	10	10	100.00	-	-	-	-	-	-	-	-	-	-
UART	439	453	96.91	96.88	92.64	99.44	98.56	-	99.48	98.14	98.25	74.67	-
USBDEV	1754	1780	98.54	97.14	95.95	98.19	97.29	-	98.79	98.34	95.53	95.54	91.53
XBAR_MAIN	450	450	100.00	99.34	99.09	100.00	98.92	-	100.00	100.00	96.75	99.63	-
XBAR_PERI	450	450	100.00	99.53	99.13	100.00	99.45	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim