Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	15	25	60.00	65.44	91.41	12.84	92.06	-	97.97	96.23	85.65	98.82	78.38
AES/MASKED	30	32	93.75	88.70	93.71	74.00	98.38	94.19	95.86	86.92	-	97.99	94.07
AES/UNMASKED	28	32	87.50	86.73	89.03	73.42	97.73	89.45	91.95	79.50	-	97.99	86.67
ALERT_HANDLER	24	26	92.31	90.98	92.24	82.30	98.40	-	99.70	98.57	92.98	90.92	79.03
AON_TIMER	23	23	100.00	96.09	98.69	92.91	96.67	-	99.09	98.56	99.05	98.04	-
CHIP	252	328	76.83	80.21	84.67	58.48	97.49	-	94.54	93.94	90.47	87.26	57.14
CLKMGR	25	27	92.59	92.32	97.94	84.39	94.63	-	98.97	98.64	92.90	99.19	100.00
CSRNG	16	19	84.21	87.56	94.81	72.45	95.41	97.05	97.87	92.77	-	93.37	95.24
EDN/EDN0	21	21	100.00	85.89	79.04	82.74	95.88	-	96.90	89.40	85.61	76.51	46.77
EDN/EDN1	21	21	100.00	87.07	83.45	79.83	97.92	-	97.88	92.42	88.54	95.25	43.18
ENTROPY_SRC/RNG_4BITS	21	23	91.30	73.27	88.23	47.51	84.07	94.30	97.01	86.47	-	76.72	92.71
FLASH_CTRL	77	79	97.47	95.80	94.33	96.04	97.02	-	95.93	97.10	93.63	97.23	87.76
GPIO	25	27	92.59	97.35	93.94	100.00	98.10	-	99.76	99.80	98.13	78.07	-
HMAC	28	28	100.00	79.89	97.69	44.39	97.60	-	99.64	98.84	95.84	100.00	94.12
I2C	44	50	88.00	87.65	82.50	83.40	97.04	-	96.69	93.04	87.86	89.66	45.24
KEYMGR	29	30	96.67	85.51	94.80	64.02	97.72	-	98.76	96.26	92.00	96.26	90.70
KMAC/MASKED	30	40	75.00	81.50	69.71	77.87	96.91	-	96.14	90.31	86.36	29.56	46.20
KMAC/UNMASKED	29	40	72.50	78.85	66.23	73.82	96.50	-	92.84	87.13	83.74	27.28	40.15
LC_CTRL/VOLATILE_UNLOCK_DISABLED	39	39	100.00	90.48	83.82	93.06	94.55	-	97.20	93.70	78.94	86.63	62.62
LC_CTRL/VOLATILE_UNLOCK_ENABLED	39	39	100.00	90.03	83.08	92.88	94.13	-	97.09	93.37	79.06	84.22	61.68
OTBN	40	42	95.24	87.87	81.00	94.92	87.68	97.66	97.86	81.57	-	81.18	63.38
OTP_CTRL	28	30	93.33	82.10	77.79	74.00	94.50	-	88.54	83.55	90.18	82.56	44.10
PRIM_ALERT	5	5	100.00	90.05	94.05	-	86.05	-	100.00	95.83	95.83	100.00	78.57
PRIM_ESC	1	1	100.00	83.86	82.54	-	85.19	-	88.99	77.78	78.05	100.00	67.86
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	26	29	89.66	96.32	92.99	98.85	97.13	-	99.09	96.18	96.04	99.62	74.00
ROM_CTRL/32KB	18	19	94.74	93.73	97.07	87.59	96.52	-	99.33	99.27	98.22	95.18	93.33
ROM_CTRL/64KB	18	19	94.74	96.86	97.01	96.18	97.39	-	99.46	99.27	97.47	95.52	93.33
RSTMGR	19	19	100.00	97.76	99.23	95.52	98.53	-	99.51	99.83	98.61	98.99	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	50	53	94.34	77.39	84.82	51.72	95.63	-	94.78	87.83	87.50	69.57	84.42
RV_TIMER	17	19	89.47	94.71	94.66	92.65	96.82	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	31	33	93.94	86.99	90.78	74.80	95.40	-	98.88	98.25	96.21	71.19	89.36
SPI_HOST	26	26	100.00	92.27	91.30	89.50	96.03	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	28	31	90.32	95.52	94.95	94.20	97.41	95.09	95.72	92.23	-	91.84	100.00
SRAM_CTRL/RET	28	31	90.32	91.90	81.75	96.00	97.94	93.02	94.09	87.95	-	78.31	66.67
SYSRST_CTRL	27	27	100.00	83.79	91.64	67.68	92.05	-	96.46	96.92	93.90	99.77	71.15
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	26	27	96.30	83.94	95.93	57.33	98.56	-	99.17	97.44	95.57	91.55	-
USBDEV	98	100	98.00	88.10	93.47	73.71	97.11	-	98.56	97.95	93.95	97.23	79.66
XBAR_MAIN	18	18	100.00	84.64	99.16	56.63	98.14	-	100.00	100.00	96.62	100.00	-
XBAR_PERI	18	18	100.00	77.10	99.13	34.04	98.13	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim