Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	15	25	60.00	66.16	93.17	12.77	92.54	-	98.86	97.40	87.22	98.58	83.78
AES/MASKED	28	32	87.50	88.35	94.17	72.66	98.23	94.30	95.94	87.20	-	97.99	95.56
AES/UNMASKED	29	32	90.62	87.51	89.66	75.14	97.73	89.54	91.74	80.02	-	97.99	88.89
ALERT_HANDLER	23	26	88.46	88.32	90.30	76.35	98.31	-	99.72	97.99	90.59	84.19	79.03
AON_TIMER	23	23	100.00	98.00	99.05	96.85	98.10	-	99.09	98.56	99.05	99.50	-
CHIP	255	328	77.74	75.37	84.35	44.27	97.49	-	94.37	93.77	89.08	87.38	57.14
CLKMGR	25	27	92.59	91.46	97.41	83.88	93.08	-	98.83	98.32	89.88	100.00	100.00
CSRNG	17	19	89.47	85.89	92.31	70.81	94.54	96.95	97.73	92.43	-	93.37	85.71
EDN/EDN0	21	21	100.00	88.49	85.46	81.75	98.26	-	98.37	94.70	89.20	91.80	53.23
EDN/EDN1	21	21	100.00	87.27	83.92	79.20	98.70	-	98.18	93.51	88.62	94.99	44.32
ENTROPY_SRC/RNG_4BITS	21	23	91.30	75.79	88.33	54.49	84.56	94.28	96.96	86.36	-	76.25	93.75
FLASH_CTRL	78	79	98.73	94.46	93.05	95.79	94.55	-	95.90	96.69	93.34	94.96	84.35
GPIO	25	27	92.59	97.48	94.01	100.00	98.42	-	99.76	99.80	98.85	77.63	-
HMAC	28	28	100.00	79.01	97.41	42.24	97.38	-	99.54	98.51	95.11	99.77	94.12
I2C	41	50	82.00	85.13	78.34	79.81	97.25	-	96.38	92.26	84.86	74.17	44.05
KEYMGR	28	30	93.33	79.58	92.05	49.21	97.49	-	98.76	97.81	93.48	84.13	86.05
KMAC/MASKED	30	40	75.00	80.63	68.35	76.49	97.05	-	95.43	89.44	83.60	29.00	44.30
KMAC/UNMASKED	30	40	75.00	79.14	66.68	74.23	96.50	-	92.84	87.43	84.63	27.62	40.88
LC_CTRL/VOLATILE_UNLOCK_DISABLED	37	39	94.87	90.90	83.59	94.13	94.97	-	97.11	93.70	78.80	83.83	64.49
LC_CTRL/VOLATILE_UNLOCK_ENABLED	39	39	100.00	90.60	84.43	93.24	94.13	-	97.22	93.66	79.41	87.38	64.49
OTBN	41	42	97.62	90.07	81.85	98.31	90.04	97.72	97.92	81.81	-	81.46	66.20
OTP_CTRL	29	30	96.67	84.07	80.80	76.54	94.88	-	88.74	84.63	93.01	90.90	46.70
PRIM_ALERT	5	5	100.00	90.76	95.47	-	86.05	-	100.00	95.83	95.83	100.00	85.71
PRIM_ESC	1	1	100.00	83.55	81.91	-	85.19	-	88.07	75.56	78.05	100.00	67.86
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	28	29	96.55	97.78	97.39	97.53	98.43	-	99.09	96.18	96.04	99.62	96.00
ROM_CTRL/32KB	18	19	94.74	96.50	96.65	95.47	97.39	-	99.19	98.54	97.03	95.18	93.33
ROM_CTRL/64KB	18	19	94.74	97.29	97.01	97.61	97.24	-	99.33	98.91	97.92	95.57	93.33
RSTMGR	19	19	100.00	98.42	99.33	97.01	98.93	-	99.51	99.83	98.47	99.50	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	52	53	98.11	76.41	85.68	48.17	95.39	-	95.57	89.17	88.75	69.19	85.71
RV_TIMER	16	19	84.21	96.32	94.66	95.88	98.41	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	31	33	93.94	81.90	90.58	59.97	95.15	-	98.84	98.13	95.84	70.75	89.36
SPI_HOST	26	26	100.00	92.17	91.25	88.66	96.60	96.96	98.76	93.35	-	72.90	100.00
SRAM_CTRL/MAIN	28	31	90.32	95.38	95.57	92.60	97.96	95.90	96.68	93.85	-	91.74	100.00
SRAM_CTRL/RET	28	31	90.32	90.75	82.37	91.80	98.08	93.83	94.99	89.51	-	78.31	66.67
SYSRST_CTRL	26	27	96.30	83.55	93.89	61.07	95.69	-	97.93	97.92	95.25	98.86	79.49
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	26	27	96.30	82.02	96.77	50.73	98.56	-	99.48	98.14	97.90	91.55	-
USBDEV	97	100	97.00	88.61	93.93	74.61	97.29	-	98.58	98.00	94.59	97.13	81.36
XBAR_MAIN	18	18	100.00	84.73	99.14	56.77	98.28	-	100.00	100.00	96.57	100.00	-
XBAR_PERI	18	18	100.00	76.68	99.13	32.33	98.58	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim