Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	15	25	60.00	65.89	92.78	12.99	91.90	-	98.13	96.41	86.27	99.29	83.78
AES/MASKED	29	32	90.62	88.10	94.19	71.89	98.23	94.31	95.95	87.24	-	97.99	95.56
AES/UNMASKED	30	32	93.75	87.22	89.54	74.57	97.54	90.08	92.55	80.96	-	97.99	86.67
ALERT_HANDLER	23	26	88.46	89.76	91.02	80.04	98.21	-	99.68	98.40	91.81	89.40	75.81
AON_TIMER	23	23	100.00	95.85	99.15	90.29	98.10	-	99.09	98.56	98.93	100.00	-
CHIP	247	328	75.30	76.28	84.28	47.18	97.37	-	94.28	93.70	89.20	87.10	57.14
CLKMGR	24	27	88.89	92.76	98.29	84.22	95.76	-	98.95	98.48	94.81	99.19	100.00
CSRNG	18	19	94.74	86.46	92.25	74.33	92.79	96.89	97.66	92.26	-	93.37	85.71
EDN/EDN0	21	21	100.00	86.32	81.90	80.95	96.10	-	97.34	90.93	85.32	86.43	49.46
EDN/EDN1	21	21	100.00	87.29	83.14	80.04	98.70	-	98.25	93.72	90.23	86.91	46.59
ENTROPY_SRC/RNG_4BITS	21	23	91.30	73.99	88.26	50.94	82.76	94.38	97.11	86.53	-	75.66	93.75
FLASH_CTRL	78	79	98.73	95.51	94.08	95.42	97.02	-	95.97	97.10	93.40	97.54	86.39
GPIO	25	27	92.59	96.79	93.54	100.00	96.84	-	99.76	99.80	97.41	77.20	-
HMAC	28	28	100.00	79.91	97.73	44.39	97.60	-	99.69	99.01	95.84	100.00	94.12
I2C	43	50	86.00	86.52	80.92	80.97	97.67	-	95.95	91.63	85.12	89.66	42.26
KEYMGR	30	30	100.00	87.46	95.25	69.65	97.49	-	98.84	97.81	94.16	97.07	88.37
KMAC/MASKED	30	40	75.00	82.21	70.03	78.70	97.89	-	96.20	90.49	86.79	29.19	47.47
KMAC/UNMASKED	31	40	77.50	81.68	67.70	79.25	98.10	-	94.07	89.04	86.15	27.62	41.61
LC_CTRL/VOLATILE_UNLOCK_DISABLED	38	39	97.44	90.55	83.80	92.88	94.97	-	97.20	93.56	79.15	85.53	63.55
LC_CTRL/VOLATILE_UNLOCK_ENABLED	38	39	97.44	90.57	83.50	93.24	94.97	-	97.17	93.66	78.78	84.35	63.55
OTBN	41	42	97.62	89.79	81.88	97.46	90.04	97.76	97.95	82.08	-	81.29	66.20
OTP_CTRL	28	30	93.33	82.26	78.90	73.20	94.69	-	88.65	83.45	90.16	85.19	47.05
PRIM_ALERT	5	5	100.00	90.20	94.34	-	86.05	-	100.00	95.83	93.75	100.00	82.14
PRIM_ESC	1	1	100.00	83.55	81.91	-	85.19	-	88.07	75.56	78.05	100.00	67.86
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	28	29	96.55	97.36	97.48	97.20	97.39	-	99.09	96.37	96.32	99.62	96.00
ROM_CTRL/32KB	18	19	94.74	97.58	98.33	97.61	96.81	-	99.33	99.27	97.77	95.27	100.00
ROM_CTRL/64KB	18	19	94.74	96.99	96.97	96.90	97.10	-	99.33	99.27	98.07	94.84	93.33
RSTMGR	19	19	100.00	98.62	99.33	98.01	98.53	-	99.51	99.83	98.82	99.16	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	51	53	96.23	77.38	86.05	50.30	95.79	-	95.46	89.00	88.75	70.03	87.01
RV_TIMER	16	19	84.21	93.38	94.66	87.06	98.41	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	31	33	93.94	85.10	90.59	69.30	95.40	-	98.82	98.11	95.45	71.19	89.36
SPI_HOST	26	26	100.00	91.60	91.30	88.24	95.27	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	28	31	90.32	95.93	94.93	95.17	97.69	95.03	95.65	92.23	-	91.84	100.00
SRAM_CTRL/RET	28	31	90.32	91.54	82.35	95.00	97.26	93.76	94.91	89.51	-	78.31	66.67
SYSRST_CTRL	27	27	100.00	87.42	93.26	74.36	94.64	-	97.71	97.59	95.36	100.00	75.64
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	24	27	88.89	76.02	90.04	40.90	97.12	-	98.86	95.80	91.02	74.49	-
USBDEV	98	100	98.00	88.42	93.91	74.07	97.29	-	98.64	98.08	94.22	97.23	81.36
XBAR_MAIN	18	18	100.00	85.02	99.11	57.97	97.98	-	100.00	100.00	96.45	100.00	-
XBAR_PERI	18	18	100.00	78.39	99.13	37.59	98.46	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim