Simulation Results: top_earlgrey_batch_sim

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 JSON Branch: master
Block Tests Coverage Summary Code Coverage
Pass Total % Overall Code Functional Assertion Block Line Branch Condition Toggle FSM
ADC_CTRL
25 25 100.00 71.00 97.82 18.59 96.60 - 99.02 98.45 94.33 100.00 97.30
AES/MASKED
30 32 93.75 89.59 94.25 76.29 98.23 94.38 95.99 87.45 - 97.99 95.56
AES/UNMASKED
30 32 93.75 87.85 89.54 75.91 98.11 89.97 92.47 81.03 - 97.99 86.67
ALERT_HANDLER
24 26 92.31 90.35 92.74 79.98 98.33 - 99.68 98.70 92.95 91.72 80.65
AON_TIMER
23 23 100.00 95.58 99.15 89.50 98.10 - 99.09 98.56 98.93 100.00 -
CHIP
253 308 82.14 71.38 76.07 41.34 96.74 - 93.68 93.28 89.52 70.52 33.33
CLKMGR
24 27 88.89 93.51 98.25 86.79 95.48 - 99.00 98.64 94.40 99.19 100.00
CSRNG
18 19 94.74 89.16 92.31 80.19 94.98 96.99 97.69 92.51 - 93.31 85.71
EDN/EDN0
21 21 100.00 83.37 76.56 78.77 94.79 - 96.14 86.75 82.30 69.78 47.85
EDN/EDN1
21 21 100.00 86.30 82.57 79.20 97.14 - 98.18 93.29 89.85 87.23 44.32
ENTROPY_SRC/RNG_4BITS
21 23 91.30 73.49 87.09 49.47 83.91 94.17 97.01 85.93 - 75.86 89.58
GPIO
25 27 92.59 97.27 94.05 99.99 97.78 - 99.76 99.80 98.27 78.35 -
HMAC
28 28 100.00 75.60 87.45 43.05 96.29 - 99.59 98.70 95.74 46.17 97.06
I2C
42 50 84.00 85.37 78.32 80.55 97.25 - 96.38 92.26 85.04 73.87 44.05
KEYMGR_DPE/EARLGREY
12 14 85.71 64.77 82.57 14.53 97.21 - 97.48 93.67 86.55 59.49 75.68
KMAC/MASKED
30 40 75.00 80.42 66.25 80.91 94.09 - 97.18 90.32 84.50 23.15 36.08
KMAC/UNMASKED
29 40 72.50 78.40 63.68 77.07 94.45 - 95.50 88.21 82.55 21.49 30.66
LC_CTRL/VOLATILE_UNLOCK_DISABLED
39 39 100.00 91.01 84.52 94.09 94.41 - 97.20 93.76 79.59 86.65 65.42
LC_CTRL/VOLATILE_UNLOCK_ENABLED
39 39 100.00 90.05 84.02 91.58 94.55 - 97.17 93.57 79.15 86.66 63.55
OTBN
40 42 95.24 91.02 86.17 97.03 89.86 99.23 99.44 94.43 - 84.62 66.20
OTP_CTRL
28 30 93.33 81.48 77.99 72.02 94.44 - 88.90 84.54 92.59 80.15 43.75
PRIM_ALERT
4 5 80.00 89.84 93.63 - 86.05 - 100.00 95.83 93.75 100.00 78.57
PRIM_ESC
1 1 100.00 85.11 85.04 - 85.19 - 90.83 80.00 82.93 100.00 71.43
PRIM_LFSR
4 4 100.00 97.07 99.14 - 95.00 - 100.00 100.00 96.55 100.00 -
PRIM_PRESENT
1 1 100.00 89.63 79.26 - 100.00 - 90.41 75.00 75.00 76.63 -
PRIM_PRINCE
1 1 100.00 100.00 100.00 - 100.00 - 100.00 100.00 100.00 100.00 -
PWRMGR
23 29 79.31 96.31 94.64 96.38 97.91 - 98.93 95.62 94.63 90.02 94.00
ROM_CTRL/192KB
18 19 94.74 95.64 92.74 96.64 97.53 - 98.95 98.56 97.77 95.10 73.33
RSTMGR
19 19 100.00 98.38 99.22 97.26 98.66 - 99.51 99.83 98.47 99.08 -
RSTMGR_CNSTY_CHK
1 1 100.00 97.81 95.61 - 100.00 - 98.46 98.39 88.89 100.00 92.31
RV_DM/USE_JTAG_INTERFACE
50 53 94.34 75.38 85.29 45.31 95.55 - 95.57 88.41 89.03 70.32 83.12
RV_TIMER
17 19 89.47 96.49 94.66 97.35 97.45 - 100.00 100.00 100.00 78.66 -
SPI_DEVICE/1R1W
31 33 93.94 87.82 91.19 76.88 95.40 - 98.87 98.20 95.52 73.99 89.36
SPI_HOST
26 26 100.00 91.41 91.14 87.82 95.27 96.78 98.54 92.95 - 73.07 100.00
SRAM_CTRL/MAIN
29 31 93.55 94.25 94.32 90.60 97.83 93.47 94.53 90.91 - 91.84 100.00
SRAM_CTRL/RET
29 31 93.55 90.51 81.46 92.80 97.26 91.78 93.41 87.44 - 78.32 66.67
SYSRST_CTRL
27 27 100.00 82.15 90.93 64.90 90.62 - 96.15 96.74 93.80 100.00 67.95
TL_AGENT
1 1 100.00 - - - - - - - - - -
UART
26 27 96.30 84.34 92.58 62.46 97.98 - 99.48 98.14 98.02 74.67 -
USBDEV
97 100 97.00 88.68 93.77 74.98 97.29 - 98.56 97.87 94.23 96.82 81.36
XBAR_MAIN
18 18 100.00 79.32 99.06 41.08 97.82 - 100.00 100.00 96.88 99.37 -
XBAR_PERI
18 18 100.00 77.67 99.13 35.22 98.65 - 100.00 100.00 96.51 100.00 -