Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	16	25	64.00	65.64	92.13	12.89	91.90	-	98.00	96.29	86.23	99.05	81.08
AES/MASKED	29	32	90.62	89.08	93.69	75.33	98.23	94.34	96.07	87.37	-	97.99	93.33
AES/UNMASKED	29	32	90.62	87.34	89.73	74.57	97.73	89.65	92.00	80.06	-	97.99	88.89
ALERT_HANDLER	25	26	96.15	90.54	90.53	83.06	98.04	-	99.61	98.41	92.86	87.60	74.19
AON_TIMER	23	23	100.00	96.27	99.12	91.60	98.10	-	99.09	98.56	98.81	100.00	-
CHIP	251	329	76.29	75.41	84.56	44.18	97.49	-	94.25	93.66	89.22	88.51	57.14
CLKMGR	25	27	92.59	93.36	98.20	86.11	95.76	-	98.95	98.48	94.36	99.19	100.00
CSRNG	17	19	89.47	88.91	92.36	79.84	94.54	97.05	97.73	92.68	-	93.31	85.71
EDN/EDN0	20	21	95.24	82.12	73.70	79.17	93.49	-	95.60	84.94	80.50	66.60	40.86
EDN/EDN1	21	21	100.00	87.56	84.63	79.62	98.44	-	98.18	93.29	88.77	95.19	47.73
ENTROPY_SRC/RNG_4BITS	21	23	91.30	74.80	88.25	51.92	84.24	94.41	97.11	86.53	-	75.60	93.75
FLASH_CTRL	78	79	98.73	95.17	93.83	94.74	96.94	-	95.97	97.08	93.84	97.91	84.35
GPIO	25	27	92.59	98.52	97.12	100.00	98.42	-	99.76	99.80	98.70	90.24	-
HMAC	28	28	100.00	79.87	97.95	44.07	97.60	-	99.69	99.50	96.46	100.00	94.12
I2C	43	50	86.00	86.18	81.49	79.60	97.46	-	96.45	92.41	85.34	88.61	44.64
KEYMGR	29	30	96.67	83.31	94.84	57.61	97.49	-	98.76	97.63	93.72	95.70	88.37
KMAC/MASKED	31	40	77.50	80.66	68.59	76.76	96.62	-	95.41	89.32	84.65	29.27	44.30
KMAC/UNMASKED	29	40	72.50	78.94	66.36	73.96	96.50	-	92.81	86.90	83.14	27.34	41.61
LC_CTRL/VOLATILE_UNLOCK_DISABLED	38	39	97.44	90.13	83.74	92.53	94.13	-	97.20	93.70	79.22	85.97	62.62
LC_CTRL/VOLATILE_UNLOCK_ENABLED	38	39	97.44	90.94	83.81	94.31	94.69	-	97.04	93.08	78.58	86.81	63.55
OTBN	40	42	95.24	93.95	94.16	97.88	89.82	99.33	99.49	91.59	-	87.99	97.56
OTP_CTRL	28	30	93.33	82.96	78.10	75.89	94.88	-	88.60	83.55	90.29	82.22	45.83
PRIM_ALERT	4	5	80.00	90.20	94.34	-	86.05	-	100.00	95.83	93.75	100.00	82.14
PRIM_ESC	1	1	100.00	84.80	84.41	-	85.19	-	89.91	77.78	82.93	100.00	71.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWM	17	17	100.00	97.80	96.19	98.02	99.20	99.05	99.36	98.33	-	90.87	-
PWRMGR	28	29	96.55	97.49	97.33	98.02	97.13	-	99.09	96.18	95.76	99.62	96.00
ROM_CTRL/32KB	18	19	94.74	97.00	96.98	97.37	96.66	-	99.46	98.91	97.77	95.44	93.33
ROM_CTRL/64KB	18	19	94.74	96.11	95.28	95.94	97.10	-	99.19	98.54	97.03	94.96	86.67
RSTMGR	19	19	100.00	98.28	99.31	97.01	98.53	-	99.51	99.83	98.75	99.16	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	52	53	98.11	78.19	85.70	53.08	95.79	-	95.09	88.67	88.61	73.00	83.12
RV_TIMER	15	19	78.95	95.93	100.00	89.71	98.09	-	100.00	100.00	100.00	100.00	-
SPI_DEVICE/1R1W	31	33	93.94	84.08	93.05	63.79	95.40	-	98.83	98.11	95.96	83.01	89.36
SPI_HOST	25	26	96.15	91.22	91.09	88.24	94.33	96.60	98.76	92.55	-	73.07	100.00
SRAM_CTRL/MAIN	28	31	90.32	95.39	94.75	93.60	97.82	94.96	95.50	91.91	-	91.60	100.00
SRAM_CTRL/RET	26	31	83.87	91.37	82.03	94.40	97.67	93.42	94.39	88.73	-	78.31	66.67
SYSRST_CTRL	27	27	100.00	83.17	92.13	65.03	92.34	-	96.84	97.18	94.85	100.00	71.79
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	26	27	96.30	86.00	95.96	64.93	97.12	-	99.17	96.97	96.15	91.55	-
USBDEV	98	100	98.00	87.81	94.06	72.08	97.29	-	98.64	98.08	94.24	96.28	83.05
XBAR_MAIN	18	18	100.00	82.96	99.12	51.80	97.95	-	100.00	100.00	96.50	100.00	-
XBAR_PERI	18	18	100.00	80.46	99.13	43.84	98.41	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim