Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	138	233	59.23	67.56	96.19	13.79	92.71	-	98.89	97.46	87.55	99.76	97.30
AES/MASKED	1029	1110	92.70	97.37	96.59	97.13	98.38	96.91	97.79	92.71	-	98.08	97.78
AES/UNMASKED	976	1110	87.93	96.14	93.00	97.32	98.11	94.01	95.29	87.62	-	97.99	91.11
ALERT_HANDLER	533	593	89.88	99.01	98.91	99.23	98.88	-	99.99	99.99	97.52	97.03	100.00
AON_TIMER	180	180	100.00	99.09	99.17	100.00	98.10	-	99.09	98.56	99.05	100.00	-
CHIP	1725	2008	85.91	94.38	85.80	99.35	97.99	-	94.85	94.74	93.28	88.97	57.14
CLKMGR	238	273	87.18	93.87	98.55	87.31	95.76	-	99.07	98.74	95.77	99.19	100.00
CSRNG	1357	1403	96.72	94.38	96.17	89.80	97.16	98.49	99.50	96.30	-	93.64	95.24
EDN/EDN0	678	688	98.55	95.69	95.74	92.86	98.48	-	98.91	96.51	94.20	97.12	91.94
EDN/EDN1	676	688	98.26	95.43	95.62	92.23	98.44	-	98.48	94.59	94.62	96.08	94.32
ENTROPY_SRC/RNG_4BITS	2393	2453	97.55	90.89	90.78	92.57	89.33	95.18	97.84	88.06	-	79.30	97.92
FLASH_CTRL	1141	1154	98.87	97.10	95.93	98.42	96.94	-	96.12	97.47	94.90	98.66	92.52
GPIO	230	253	90.91	97.66	94.88	100.00	98.10	-	99.76	99.80	99.57	80.38	-
HMAC	694	694	100.00	98.61	98.61	99.62	97.60	-	99.74	99.67	96.57	100.00	97.06
I2C	593	755	78.54	89.02	80.28	89.11	97.67	-	97.25	93.75	89.14	73.65	47.62
KEYMGR	638	653	97.70	95.88	98.85	91.06	97.72	-	99.20	99.00	98.24	97.80	100.00
KMAC/MASKED	339	540	62.78	86.48	74.54	86.31	98.59	-	97.15	92.90	90.37	29.62	62.66
KMAC/UNMASKED	336	540	62.22	85.25	72.10	85.10	98.54	-	95.33	91.65	90.35	27.71	55.47
LC_CTRL/VOLATILE_UNLOCK_DISABLED	513	523	98.09	92.44	85.92	96.44	94.97	-	97.28	94.00	81.84	88.25	68.22
LC_CTRL/VOLATILE_UNLOCK_ENABLED	514	523	98.28	92.18	85.75	96.09	94.69	-	97.26	93.80	81.20	88.25	68.22
OTBN	418	436	95.87	95.73	95.91	100.00	91.29	99.47	99.59	93.25	-	93.24	97.56
OTP_CTRL	801	903	88.70	91.39	86.21	92.45	95.52	-	90.40	86.94	94.05	96.12	63.54
PRIM_ALERT	58	60	96.67	91.33	96.61	-	86.05	-	100.00	95.83	97.92	100.00	89.29
PRIM_ESC	20	20	100.00	89.45	93.71	-	85.19	-	95.41	88.89	87.80	100.00	96.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	10	10	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWM	189	189	100.00	98.23	96.81	98.68	99.20	99.80	99.81	99.74	-	90.87	-
PWRMGR	259	273	94.87	98.41	97.54	99.01	98.69	-	99.09	96.37	96.61	99.62	96.00
ROM_CTRL/32KB	150	156	96.15	98.52	98.68	99.05	97.82	-	99.46	100.00	98.37	95.57	100.00
ROM_CTRL/64KB	153	156	98.08	98.47	98.68	99.05	97.68	-	99.46	100.00	98.37	95.57	100.00
RSTMGR	147	148	99.32	99.12	99.66	98.76	98.93	-	99.51	99.83	99.31	100.00	-
RSTMGR_CNSTY_CHK	8	10	80.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	335	368	91.03	79.39	89.28	52.71	96.18	-	96.25	90.50	90.42	77.04	92.21
RV_TIMER	179	223	80.27	97.70	94.66	99.71	98.73	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	395	416	94.95	95.13	90.85	99.01	95.52	-	98.90	98.30	96.51	71.19	89.36
SPI_HOST	217	220	98.64	92.57	91.30	90.76	95.65	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	224	248	90.32	96.85	95.85	96.60	98.10	96.30	97.05	94.50	-	91.84	100.00
SRAM_CTRL/RET	222	248	89.52	92.53	82.50	97.00	98.08	94.03	95.21	89.83	-	78.31	66.67
SYSRST_CTRL	401	410	97.80	96.11	98.05	91.43	98.85	-	98.92	99.04	98.04	100.00	94.23
TL_AGENT	10	10	100.00	-	-	-	-	-	-	-	-	-	-
UART	438	453	96.69	96.96	92.64	99.39	98.85	-	99.48	98.14	98.25	74.67	-
USBDEV	1756	1780	98.65	97.44	96.66	98.37	97.29	-	98.79	98.34	95.50	95.74	94.92
XBAR_MAIN	450	450	100.00	99.33	99.17	100.00	98.80	-	100.00	100.00	96.70	100.00	-
XBAR_PERI	450	450	100.00	99.60	99.16	100.00	99.65	-	100.00	100.00	96.64	100.00	-

Simulation Results: top_earlgrey_batch_sim