Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	136	233	58.37	67.44	96.15	13.64	92.54	-	98.89	97.46	87.55	99.53	97.30
AES/MASKED	1017	1110	91.62	97.42	96.57	97.32	98.38	96.92	97.77	92.73	-	97.99	97.78
AES/UNMASKED	1023	1110	92.16	96.07	92.98	97.32	97.92	93.93	95.22	87.50	-	98.08	91.11
ALERT_HANDLER	535	593	90.22	98.97	98.90	99.14	98.87	-	99.97	99.97	97.52	97.04	100.00
AON_TIMER	180	180	100.00	98.93	98.69	100.00	98.10	-	99.09	98.56	99.05	98.04	-
CHIP	1712	2005	85.39	94.25	85.41	99.46	97.87	-	94.68	94.60	92.92	87.73	57.14
CLKMGR	230	273	84.25	93.87	98.53	87.31	95.76	-	99.07	98.74	95.64	99.19	100.00
CSRNG	1354	1403	96.51	94.69	96.17	90.97	96.94	98.49	99.50	96.30	-	93.64	95.24
EDN/EDN0	675	688	98.11	95.64	95.35	92.66	98.92	-	98.86	96.23	93.67	97.12	90.86
EDN/EDN1	670	688	97.38	95.68	95.89	92.44	98.70	-	98.48	94.59	94.77	96.15	95.45
ENTROPY_SRC/RNG_4BITS	2394	2453	97.59	90.95	90.73	92.30	89.82	95.21	97.84	88.12	-	79.04	97.92
FLASH_CTRL	1143	1154	99.05	97.08	95.78	98.45	97.02	-	96.10	97.42	94.88	98.66	91.84
GPIO	235	253	92.89	98.96	98.14	100.00	98.73	-	99.76	99.80	99.57	93.43	-
HMAC	694	694	100.00	98.86	99.20	99.79	97.60	-	99.74	99.67	96.57	100.00	100.00
I2C	598	755	79.21	89.12	80.57	89.11	97.67	-	97.37	93.90	89.18	74.17	48.21
KEYMGR	641	653	98.16	95.92	98.79	91.26	97.72	-	99.20	99.00	98.08	97.68	100.00
KMAC/MASKED	337	540	62.41	86.19	74.51	85.62	98.45	-	97.12	92.84	90.30	29.62	62.66
KMAC/UNMASKED	336	540	62.22	85.57	73.21	85.24	98.25	-	95.73	92.11	90.57	27.81	59.85
LC_CTRL/VOLATILE_UNLOCK_DISABLED	516	523	98.66	92.38	85.90	96.26	94.97	-	97.28	94.00	81.77	88.25	68.22
LC_CTRL/VOLATILE_UNLOCK_ENABLED	513	523	98.09	92.35	86.12	96.09	94.83	-	97.26	94.09	81.82	88.25	69.16
OTBN	421	436	96.56	94.89	87.13	100.00	97.54	99.38	99.56	95.45	-	85.91	67.61
OTP_CTRL	803	903	88.93	91.31	86.10	92.30	95.52	-	90.43	86.94	94.05	95.73	63.37
PRIM_ALERT	57	60	95.00	91.54	97.02	-	86.05	-	100.00	95.83	100.00	100.00	89.29
PRIM_ESC	20	20	100.00	89.45	93.71	-	85.19	-	95.41	88.89	87.80	100.00	96.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	10	10	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	260	273	95.24	98.50	97.54	99.01	98.96	-	99.09	96.37	96.61	99.62	96.00
ROM_CTRL/32KB	154	156	98.72	98.53	98.77	99.28	97.53	-	99.46	100.00	98.81	95.57	100.00
ROM_CTRL/64KB	154	156	98.72	98.40	98.77	99.05	97.39	-	99.46	100.00	98.81	95.57	100.00
RSTMGR	148	148	100.00	99.12	99.66	98.76	98.93	-	99.51	99.83	99.31	100.00	-
RSTMGR_CNSTY_CHK	7	10	70.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	331	368	89.95	79.06	88.69	52.38	96.10	-	96.25	90.50	90.42	71.45	94.81
RV_TIMER	183	223	82.06	97.50	94.66	99.12	98.73	-	100.00	100.00	100.00	78.66	-
SPI_DEVICE/1R1W	394	416	94.71	95.95	93.33	99.11	95.40	-	98.90	98.30	96.53	83.54	89.36
SPI_HOST	220	220	100.00	94.07	95.03	90.76	96.41	96.96	98.76	93.35	-	88.02	100.00
SRAM_CTRL/MAIN	224	248	90.32	96.90	95.94	96.80	97.96	96.30	97.05	94.50	-	92.22	100.00
SRAM_CTRL/RET	224	248	90.32	92.46	82.50	96.80	98.08	94.03	95.21	89.83	-	78.31	66.67
SYSRST_CTRL	392	410	95.61	95.61	97.78	90.57	98.47	-	98.92	99.00	98.01	100.00	92.95
TL_AGENT	10	10	100.00	-	-	-	-	-	-	-	-	-	-
UART	440	453	97.13	96.71	92.64	99.53	97.98	-	99.48	98.14	98.25	74.67	-
USBDEV	1758	1780	98.76	97.30	96.32	98.28	97.29	-	98.79	98.34	95.50	95.74	93.22
XBAR_MAIN	450	450	100.00	99.27	99.19	100.00	98.62	-	100.00	100.00	96.75	100.00	-
XBAR_PERI	450	450	100.00	99.51	99.13	100.00	99.39	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim