Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	15	25	60.00	65.69	92.47	12.69	91.90	-	98.03	96.29	85.69	98.58	83.78
AES/MASKED	30	32	93.75	89.14	93.66	75.53	98.23	94.38	95.90	87.41	-	97.99	93.33
AES/UNMASKED	28	32	87.50	87.71	88.91	76.48	97.73	89.25	91.64	79.35	-	97.99	86.67
ALERT_HANDLER	23	26	88.46	90.47	91.15	82.32	97.94	-	99.65	98.48	91.03	92.38	74.19
AON_TIMER	23	23	100.00	96.09	99.09	91.08	98.10	-	99.09	98.56	98.69	100.00	-
CHIP	252	329	76.60	71.18	84.45	31.59	97.49	-	94.35	93.74	88.52	88.49	57.14
CLKMGR	25	27	92.59	92.69	97.84	85.59	94.63	-	98.93	98.64	92.45	99.19	100.00
CSRNG	17	19	89.47	88.38	92.43	77.73	94.98	97.09	97.80	92.77	-	93.44	85.71
EDN/EDN0	20	21	95.24	84.20	82.04	73.61	96.96	-	97.55	91.35	83.87	83.11	54.30
EDN/EDN1	21	21	100.00	86.73	82.40	79.62	98.18	-	97.95	92.86	91.23	87.93	42.05
ENTROPY_SRC/RNG_4BITS	21	23	91.30	74.25	87.87	51.47	83.42	94.43	97.09	86.58	-	76.12	91.67
FLASH_CTRL	76	79	96.20	95.64	94.06	95.91	96.94	-	95.91	96.99	93.81	97.89	85.71
GPIO	25	27	92.59	97.36	93.97	100.00	98.10	-	99.76	99.80	98.27	78.07	-
HMAC	28	28	100.00	80.05	98.27	44.50	97.38	-	99.64	98.84	95.79	100.00	97.06
I2C	43	50	86.00	85.93	81.78	78.54	97.46	-	96.41	92.33	85.46	89.45	45.24
KEYMGR	29	30	96.67	88.09	95.28	71.51	97.49	-	98.76	97.53	94.76	96.96	88.37
KMAC/MASKED	27	40	67.50	80.13	67.16	76.76	96.48	-	95.19	88.95	83.93	29.14	38.61
KMAC/UNMASKED	29	40	72.50	78.57	65.40	73.96	96.35	-	92.87	87.28	82.99	27.34	36.50
LC_CTRL/VOLATILE_UNLOCK_DISABLED	38	39	97.44	90.24	83.71	92.88	94.13	-	97.15	93.70	79.22	85.88	62.62
LC_CTRL/VOLATILE_UNLOCK_ENABLED	38	39	97.44	90.53	84.13	92.35	95.11	-	97.22	93.66	79.54	86.66	63.55
OTBN	38	42	90.48	90.99	90.77	94.49	87.71	97.81	97.95	82.63	-	87.37	95.12
OTP_CTRL	28	30	93.33	83.95	79.70	77.34	94.82	-	88.60	83.55	90.60	90.46	45.31
PRIM_ALERT	5	5	100.00	90.76	95.47	-	86.05	-	100.00	95.83	95.83	100.00	85.71
PRIM_ESC	1	1	100.00	85.60	86.01	-	85.19	-	90.83	80.00	87.80	100.00	71.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWM	17	17	100.00	97.96	96.01	98.68	99.20	99.05	99.28	98.33	-	90.43	-
PWRMGR	28	29	96.55	98.21	97.42	98.52	98.69	-	99.09	96.37	96.04	99.62	96.00
ROM_CTRL/32KB	18	19	94.74	96.65	97.92	95.23	96.81	-	99.46	98.91	96.29	94.96	100.00
ROM_CTRL/64KB	18	19	94.74	97.08	97.07	97.37	96.81	-	99.46	99.64	97.47	95.47	93.33
RSTMGR	19	19	100.00	97.46	99.24	95.02	98.13	-	99.51	99.83	98.47	99.16	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	52	53	98.11	77.50	86.81	50.06	95.63	-	95.46	89.00	88.61	73.95	87.01
RV_TIMER	16	19	84.21	97.32	100.00	93.24	98.73	-	100.00	100.00	100.00	100.00	-
SPI_DEVICE/1R1W	31	33	93.94	87.89	90.73	77.53	95.40	-	98.84	98.11	96.17	71.19	89.36
SPI_HOST	26	26	100.00	92.33	91.30	89.08	96.60	96.96	98.76	93.35	-	73.07	100.00
SRAM_CTRL/MAIN	28	31	90.32	95.92	94.67	95.40	97.69	94.69	95.28	91.59	-	91.79	100.00
SRAM_CTRL/RET	28	31	90.32	91.00	81.00	94.60	97.39	92.00	92.97	86.07	-	78.31	66.67
SYSRST_CTRL	27	27	100.00	83.60	93.14	64.47	93.20	-	97.17	97.33	94.92	100.00	76.28
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	26	27	96.30	84.49	91.68	63.23	98.56	-	99.17	97.44	95.45	74.67	-
USBDEV	98	100	98.00	87.77	94.31	71.71	97.29	-	98.70	98.17	94.49	95.43	84.75
XBAR_MAIN	18	18	100.00	90.14	99.14	72.83	98.46	-	100.00	100.00	96.55	100.00	-
XBAR_PERI	18	18	100.00	76.91	99.13	33.47	98.12	-	100.00	100.00	96.51	100.00	-

Simulation Results: top_earlgrey_batch_sim