Simulation Results

Block	Tests			Coverage Summary				Code Coverage
Block	Pass	Total	%	Overall	Code	Functional	Assertion	Block	Line	Branch	Condition	Toggle	FSM
ADC_CTRL	15	25	60.00	65.63	92.00	12.99	91.90	-	97.97	96.23	85.90	98.82	81.08
AES/MASKED	28	32	87.50	88.88	93.47	74.95	98.23	94.05	95.75	86.80	-	97.99	93.33
AES/UNMASKED	29	32	90.62	87.23	89.56	74.19	97.92	89.40	91.73	79.65	-	97.99	88.89
ALERT_HANDLER	25	26	96.15	90.01	91.32	80.41	98.31	-	99.71	97.81	91.03	89.03	79.03
AON_TIMER	23	23	100.00	95.65	99.09	89.76	98.10	-	99.09	98.56	98.69	100.00	-
CHIP	255	328	77.74	74.11	84.53	40.44	97.37	-	94.41	94.26	89.53	87.30	57.14
CLKMGR	25	27	92.59	92.87	98.22	84.91	95.48	-	99.00	98.64	94.27	99.19	100.00
CSRNG	17	19	89.47	87.62	92.35	76.20	94.32	97.05	97.76	92.68	-	93.24	85.71
EDN/EDN0	20	21	95.24	85.05	79.18	80.95	95.01	-	97.12	89.96	85.61	75.88	47.31
EDN/EDN1	21	21	100.00	87.73	82.57	81.93	98.70	-	97.95	92.86	91.08	87.80	43.18
ENTROPY_SRC/RNG_4BITS	21	23	91.30	75.72	88.16	54.94	84.07	94.45	97.11	86.64	-	76.18	92.71
FLASH_CTRL	78	79	98.73	95.63	94.10	95.76	97.02	-	95.96	97.08	93.48	97.59	86.39
GPIO	25	27	92.59	98.41	97.13	100.00	98.10	-	99.76	99.80	98.56	90.40	-
HMAC	28	28	100.00	78.55	97.09	40.96	97.60	-	99.64	98.84	95.79	100.00	91.18
I2C	43	50	86.00	85.40	78.09	81.08	97.04	-	96.41	92.33	84.70	72.95	44.05
KEYMGR	29	30	96.67	84.11	94.82	60.02	97.49	-	98.72	97.63	93.24	96.13	88.37
KMAC/MASKED	30	40	75.00	80.76	68.61	76.76	96.91	-	95.43	89.57	84.85	28.90	44.30
KMAC/UNMASKED	29	40	72.50	80.15	67.31	75.63	97.52	-	93.83	88.20	85.56	27.34	41.61
LC_CTRL/VOLATILE_UNLOCK_DISABLED	39	39	100.00	90.32	83.95	92.88	94.13	-	97.20	93.70	79.36	86.85	62.62
LC_CTRL/VOLATILE_UNLOCK_ENABLED	38	39	97.44	90.98	84.02	93.95	94.97	-	97.00	93.08	79.34	86.19	64.49
OTBN	38	42	90.48	87.33	80.33	94.07	87.58	97.65	97.86	81.47	-	78.59	63.38
OTP_CTRL	29	30	96.67	83.36	79.69	76.40	93.99	-	88.59	83.45	90.32	89.92	46.18
PRIM_ALERT	5	5	100.00	90.55	95.06	-	86.05	-	100.00	95.83	93.75	100.00	85.71
PRIM_ESC	1	1	100.00	84.22	83.25	-	85.19	-	88.99	77.78	78.05	100.00	71.43
PRIM_LFSR	4	4	100.00	97.07	99.14	-	95.00	-	100.00	100.00	96.55	100.00	-
PRIM_PRESENT	1	1	100.00	95.88	91.76	-	100.00	-	90.41	100.00	100.00	76.63	-
PRIM_PRINCE	1	1	100.00	100.00	100.00	-	100.00	-	100.00	100.00	100.00	100.00	-
PWRMGR	27	29	93.10	95.95	91.39	98.02	98.43	-	99.09	96.37	96.32	91.15	74.00
ROM_CTRL/32KB	18	19	94.74	97.13	97.11	96.90	97.39	-	99.46	99.64	97.92	95.20	93.33
ROM_CTRL/64KB	18	19	94.74	97.51	98.09	96.90	97.53	-	99.46	98.91	97.03	95.03	100.00
RSTMGR	19	19	100.00	98.81	99.27	98.51	98.66	-	99.51	99.83	98.82	98.91	-
RSTMGR_CNSTY_CHK	1	1	100.00	97.52	95.05	-	100.00	-	98.41	98.31	86.21	100.00	92.31
RV_DM/USE_JTAG_INTERFACE	51	53	96.23	76.85	85.92	48.99	95.63	-	95.57	89.50	89.03	69.77	85.71
RV_TIMER	16	19	84.21	95.15	99.50	89.12	96.82	-	100.00	100.00	98.77	99.22	-
SPI_DEVICE/1R1W	30	33	90.91	83.80	90.72	65.28	95.40	-	98.81	98.11	96.14	71.19	89.36
SPI_HOST	26	26	100.00	92.99	95.03	88.66	95.27	96.96	98.76	93.35	-	88.02	100.00
SRAM_CTRL/MAIN	28	31	90.32	94.76	95.91	90.40	97.96	94.96	95.50	92.07	-	96.09	100.00
SRAM_CTRL/RET	27	31	87.10	91.21	83.36	93.00	97.26	93.83	94.99	89.51	-	82.28	66.67
SYSRST_CTRL	27	27	100.00	88.06	94.31	73.41	96.46	-	98.12	97.96	95.56	99.77	80.13
TL_AGENT	1	1	100.00	-	-	-	-	-	-	-	-	-	-
UART	24	27	88.89	79.75	90.78	49.63	98.85	-	98.86	96.50	93.82	73.93	-
USBDEV	97	100	97.00	87.91	93.82	72.62	97.29	-	98.62	98.04	93.95	95.43	83.05
XBAR_MAIN	18	18	100.00	91.76	99.14	77.98	98.16	-	100.00	100.00	96.55	100.00	-
XBAR_PERI	18	18	100.00	75.40	99.16	28.90	98.14	-	100.00	100.00	96.64	100.00	-

Simulation Results: top_earlgrey_batch_sim